Design space exploration for application specific FPGAS in system-on-a-chip designs

Abstract

The inclusion of field programmable gate arrays (FPGAs) within a system-on-a-chip (SOC) design offers programmability, flexibility, and reconfigurability not possible with application specific integrated circuits (ASIC) or fullcustom implementations. However, these benefits come at the expense of significant area, performance, and power consumption overheads compared to ASIC or full-custom circuits. As a typical SOC design will require fabrication of the final integrated circuit, rather than rely on a generic FPGA architecture, an FPGA integrated within an SOC design can be optimized for the specific intended application. In this paper, we present an initial design space exploration framework for generating an application specific FPGA (ASFPGA) by tailoring several FPGA architectural features for a specific hardware circuit to improve the area, delay, or energy consumption compared to traditional FPGA designs and reduce the overheads of utilizing an FPGA compared to ASIC and full custom implementations.

Dovado: An Open-Source Design Space Exploration Framework

“…Starting with a more traditional approach, Hammerquist et al [13] devised the concept of application-specific FPGAs (AFPGAs) to fill the gap between FPGAs and Application Specific Integrated Circuits (ASICs), which are much more expensive in terms of time and money to develop and implement. The exploration problem is defined as a search among architectural features to be customized.…”

“…The main difference that the reader can notice is in the high number of BRAMs compared to the others. The first solution exploits instruction and data memories size of 2 15 , while the others 2 14 and 2 13 , respectively. We can see how increasing from 2 14 to 2 15 memory sizes yield a sensible…”