Design space exploration for low-power reconfigurable fabrics

Mehta,; Hoare,; Stander,; Jones, Jones

doi:10.1109/ipdps.2006.1639484

Cited by 6 publications

(5 citation statements)

References 11 publications

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“…In paper [45], Gayatri Mehta, et.al, proposed a reconfigurable fabric models for maintain FPGAs. The authors concluded that the feature called reconfigurable is like a reprogrammable; that could be used for reducing area requirement.…”

Section: Related Workmentioning

confidence: 99%

An Exhaustive Research Survey on Vedic ALU Design

M¹

2016

IJIRCCE

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ABSTRACT:The digital India is playing an important role nowadays. Indian Vedas and Upanishads are also important and have a great history. That too Vedic mathematics was, is and will be an important basic logic for all mathematical related applications in various fields of science and technology. VLSI is an ever growing field which involves Analog, Digital and Mixed mode Designs. Also in VLSI research, an ALU is a very important system which involves user specifications while designing, for applications like microprocessor, microcontroller, signal processing and various fields. This paper concentrates on the related work on design of Vedic ALU, till date from 46 different IEEE papers and provides some common problem statements and solutions that can be used to design the best ALU, which is not done till date. Importance of reconfigurable feature is also explained in this paper.

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Section: Related Workmentioning

confidence: 99%

An Exhaustive Research Survey on Vedic ALU Design

M¹

2016

IJIRCCE

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“…In our previous research, we studied the impact of varying different design parameters such as the h of the functional units, homogeneous vs. heterogeneous functional units, various functional unit implementation techniques, granularity of the interconnect, interconnect patterns, tical routing onto physical characteristics like power, performance, and area [5,25,8,9]. We attempted to minimize the cardinality of the interconnect and the number of operations supported by each ALU, and maximize the use of dedicated pass gates in the fabri all of the optimizations a very large number of ALUs as pass remain and results appear to be area-inefficient, which motivates the idea of exploring alternative approaches in this paper.…”

Section: Domain Specific Fabricmentioning

confidence: 99%

“…Stripe-based fabrics in particular (e.g., see Figure 2) are quite promising due to their good fit to a data flow graph structure [5,25,8,9]. When a data flow graph is mapped to a stripe-style structure, however, data dependency edges often traverse multiple rows.…”

Section: Introductionmentioning

confidence: 99%

A Study of Energy-Area Tradeoffs of Various Architectural Styles for Routing Inputs in a Domain Specific Reconfigurable Fabric

Yadav

Stander

Jones

et al. 2013

VLSICS

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Coarse-grained reconfigurable fabrics (CGRF's) have great promise for achieving low-energy flexible designs for an application domain. However a universally accepted architecture for coarse-grained reconfigurable fabrics has not yet crystallized, and many architectural options are still un-der consideration by the research and industry community. One scientific question is how to efficiently route inputs through a CGRF. This paper addresses this question in part by exploring various alternative input solu-tions for a stripe-based fabric. Alternative architectural styles examined in this paper include (i) integrated constants (IC) approach where constants are loaded in the registers local to the functional units; (ii) inputs coming from the side (ICS) where both constants and variable inputs can be routed to the stripe directly where needed; (iii) ICS with extended vertical interconnect (ICS-EV); and (iv) a combination of dedicated pass gates (DPs) with standard, IC, ICS, and ICS-EV architecture styles.We implemented these architecture styles using 90 nm ASIC process from Synopsys. We perform a detailed area and energy analysis on these architectures and present quantitative results in this paper. We observed that the fabric with ICS and 50% DPs is the best among these options, providing 31% energy savings and 62% area savings over a baseline architecture for our benchmark set.

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“…Based on our initial design space exploration studies, a 4:1 interconnect was selected to create enough flexibility in the routing while reducing power consumption and delay in the fabric [12,13]. An example of this interconnection is shown in Figure 3.…”

Section: Benchmark Driven Interconnectmentioning

confidence: 99%

Interconnect Customization for a Coarse-grained Reconfigurable Fabric

Mehta

Slander

Baz

et al. 2007

2007 IEEE International Parallel and Distributed Processing Symposium

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This paper describes several system-level interconnection strategies for a coarse-grained reconfigurable fabric designed for low-energy hardware acceleration. A small, representative sub-graph for signal and image processing applications is used to predict the success of mapping larger applications onto the fabric device with these different interconnection strategies, which include 32:1, 8:1, 5:1, 4:1, 3553:1 (3:1, 5:1, 5:1, 3:1) and 355:1 (3:1, 5:1, 5:1) cardinalities. Three mapping techniques are presented and used to complete mappings onto several of these fabric instances including a mixed integer linear programming technique, a constraint programming approach, and a greedy heuristic. We present results for area (in number of required rows), power, delay, and energy as well as run times for mapping a set of signal and image processing benchmarks onto each of these interconnects. Our results indicate that the 5:1 interconnect provides the best overall results and does not require any additional hardware resources than the baseline 4:1 technique. When compared with other implementation strategies, the reconfigurable fabric energy consumption, using 5:1-based interconnect, is within 5-10X of a direct ASIC implementation, is 10X better than an Virtex II Pro FPGA and is 100X better than an Intel XScale processor.

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Design space exploration for low-power reconfigurable fabrics

Cited by 6 publications

References 11 publications

An Exhaustive Research Survey on Vedic ALU Design

An Exhaustive Research Survey on Vedic ALU Design

A Study of Energy-Area Tradeoffs of Various Architectural Styles for Routing Inputs in a Domain Specific Reconfigurable Fabric

Interconnect Customization for a Coarse-grained Reconfigurable Fabric

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