Design Space Exploration of a Sparse MobileNetV2 Using High-Level Synthesis and Sparse Matrix Techniques on FPGAs

Abstract

Convolution Neural Networks (CNNs) are gaining ground in deep learning and Artificial Intelligence (AI) domains, and they can benefit from rapid prototyping in order to produce efficient and low-power hardware designs. The inference process of a Deep Neural Network (DNN) is considered a computationally intensive process that requires hardware accelerators to operate in real-world scenarios due to the low latency requirements of real-time applications. As a result, High-Level Synthesis (HLS) tools are gaining popularity since they provide attractive ways to reduce design time complexity directly in register transfer level (RTL). In this paper, we implement a MobileNetV2 model using a state-of-the-art HLS tool in order to conduct a design space exploration and to provide insights on complex hardware designs which are tailored for DNN inference. Our goal is to combine design methodologies with sparsification techniques to produce hardware accelerators that achieve comparable error metrics within the same order of magnitude with the corresponding state-of-the-art systems while also significantly reducing the inference latency and resource utilization. Toward this end, we apply sparse matrix techniques on a MobileNetV2 model for efficient data representation, and we evaluate our designs in two different weight pruning approaches. Experimental results are evaluated with respect to the CIFAR-10 data set using several different design methodologies in order to fully explore their effects on the performance of the model under examination.

Vehicle Type Classification with Small Dataset and Transfer Learning Techniques

“…The original paper on MobileNetV2 [8] does not provide a formal architectural graph of the model; however, in a related study [10], a comprehensive architectural graph of the model has been made available.…”

Special Issue “Smart IC Design and Sensing Technologies”

“…Therefore, due to strict power and performance requirements it is very challenging to realize different digital signal processing algorithms into efficient VLSI design [19]. Designers are required to meet several constraints on power consumption, clock rate, die area, cost, and reconfigurability while also achieving balanced trade-offs between the above characteristics [20,21].…”