Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures

Hartenstein, Reiner W.; Hoffmann, Thomas; Nadeldinger, Ulrich

doi:10.1007/3-540-45373-3_12

Cited by 14 publications

(4 citation statements)

References 15 publications

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“…The most obvious approach is design space exploration [Hartenstein et al 2000;Mei et al 2005;Karuri et al 2008], which is much slower and of limited scope compared to our approach. Ansaloni et al [2008] present expression grained reconfigurable arrays, in which they customize the internal datapath of each processing element to support complex instructions, but they do not consider interconnect exploration.…”

Section: Related Workmentioning

confidence: 94%

“…However, application mapping for CGRA is still a long-running process [Mei et al 2002;Park et al 2008] despite recent advances mainly because it must involve placement and routing on a 2D array. Coupled with that, the extensive nature of CGRA design space has permitted only very limited explorations of the space so far [Mei et al 2005;Hartenstein et al 2000;Karuri et al 2008].…”

Section: Introductionmentioning

confidence: 99%

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Architecture customization of on-chip reconfigurable accelerators

Yoon

Lee

Park

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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Integrating coarse-grained reconfigurable architectures (CGRAs) into a System-on-a-Chip (SoC) presents many benefits as well as important challenges. One of the challenges is how to customize the architecture for the target applications efficiently and effectively without performing explicit design space exploration. In this article we present a novel methodology for incremental interconnect customization of CGRAs that can suggest a new interconnection architecture which is able to maximize the performance for a given set of application kernels while minimizing the hardware cost. In our methodology, we translate the problem of interconnect customization into that of inexact graph matching, and we devised a heuristic for A* search algorithm to efficiently solve the inexact graph matching problem. Our experimental results demonstrate that our customization method can quickly find application-optimized interconnections that exhibit 80% higher performance on average compared to the base architecture which has mesh interconnections, with little energy and hardware increase in interconnections and muxes.

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Section: Related Workmentioning

confidence: 94%

Section: Introductionmentioning

confidence: 99%

Architecture customization of on-chip reconfigurable accelerators

Yoon

Lee

Park

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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“…The mapping methodology is retargetable with respect to this CGRA family and it is based on a simulated annealing algorithm in which the routing of data is considered during the operations' placement phase. KressArray explorer [24] is a design exploration system aiding in the identification of architectures with optimized performance/power trade-off, however, in this work area or clock frequency issues have not been studied. In [8], a generic template for a wide range of CGRAs was presented.…”

Section: Related Workmentioning

confidence: 99%

Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays

et al. 2008

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Coarse Grain Reconfigurable Array (CGRA) architectures have been extensively used for accelerating time consuming loops. The design of such systems requires good balance between the architecture abilities and the loops' characteristics. A reliable design is characterized by optimized cost-performance trade-off. The main target of this paper is to present an exploration framework that automates the evaluation of CGRA architectures. In specific, the framework helps the designer to identify CGRA architectures tuned toward a specific application domain. The whole process is assisted: (1) by an optimized retargetable compiler based on modulo scheduling and (2) by the Synopsys Design Compiler that provides realization metrics such as the area and clock frequency. Both target on the description of a parametric CGRA architecture template which is capable of instantiating a large diversity of these architectures. Until now, many studies suggest that clock frequency influences performance. However, none of them examines the impact of architecture on clock frequency and performance. Our work studies in a unified way for the first time the area, the clock frequency, the instructions per cycle and performance. Hence, architectures with good compromise between cost and performance can be identified. Another objective of the paper is to present the advances made to the compiler approach used by the exploration framework. In specific, a new more effective priority scheme is proposed while the modulo scheduler has been equipped with backtracking capability. The experiments outline the algorithm's efficiency and scalability for a given set of DSP benchmarks. Moreover, optimized architectures with respect to cost-performance trade-off have been identified by an exploration over 72 CGRA architecture alternatives.

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“…This cycle-by-cycle reconfiguration is similar to the fetching of one VLIW instruction per cycle, but on these CGRAs the fetching is simpler as it only iterates through a loop body existing of straight-line CGRA configurations without control flow. Other CGRAs like the KressArray [24,25,26] are fully statically reconfigurable, meaning that the CGRA is configured before a loop is entered, and no reconfiguration takes place during the loop at all. Still other architectures feature a hybrid reconfigurability.…”

Section: Reconfigurabilitymentioning

confidence: 99%

Coarse-Grained Reconfigurable Array Architectures

Sutter

Raghavan

Lambrechts

2010

Handbook of Signal Processing Systems

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Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code.

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Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures

Cited by 14 publications

References 15 publications

Architecture customization of on-chip reconfigurable accelerators

Architecture customization of on-chip reconfigurable accelerators

Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays

Coarse-Grained Reconfigurable Array Architectures

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