Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling

Oppermann, Julian; Sittel, Patrick; Kumm, Martin; Reuter-Oppermann, Melanie; Koch, Andreas; Sinnen, Oliver

doi:10.1007/978-3-030-29400-7_13

Cited by 10 publications

(4 citation statements)

References 13 publications

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“…The closest related work seems to be [24]. They combine modulo scheduling and design space exploration, and solve for performance and energy efficiency, i.e., they generate a Pareto front of solutions so that the designer has a choice.…”

Section: Related Workmentioning

confidence: 99%

Integrating Energy-Optimizing Scheduling of Moldable Streaming Tasks with Design Space Exploration for Multiple Core Types on Configurable Platforms

Keller

Litzinger

Keßler

2022

J Sign Process Syst

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Design space exploration of a configurable, heterogeneous system for a given application with required throughput searches for a combination of cores or softcores with different architectures that can be accommodated within the given ASIC or FPGA area and that achieves the required throughput and optimizes power consumption. For a soft real-time streaming application, modeled as a task graph with internally parallelizable streaming tasks, this requires assigning a core type and quantity and DVFS frequency level to each task, which implies task runtime and energy consumption, and mapping and scheduling the tasks, such that the throughput requirement is met. We tightly integrate such static scheduling for stream processing applications with design space exploration of the best heterogeneous core combination, and solve the resulting combined optimization problem by an integer linear program (ILP). We evaluate our solution for different numbers of core types on synthetic and application-based task graphs, and demonstrate improvements of up to 34.8% for ARM big and LITTLE cores, and 70.5% for 3 different core types.

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Section: Related Workmentioning

confidence: 99%

Integrating Energy-Optimizing Scheduling of Moldable Streaming Tasks with Design Space Exploration for Multiple Core Types on Configurable Platforms

Keller

Litzinger

Keßler

2022

J Sign Process Syst

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“…The DFG separation proposed by [18] can benefit NIS and its MRT allocation. Modelling the nFUs as proposed in [19] can help to guarantee the selection of configurations which will not result in designs with a high latency-area product. Finally, the NIS extension to rational-IIs solutions [8] can significantly reduce the 𝑡𝑜𝑡𝑎𝑙 𝑐𝑦𝑐𝑙𝑒𝑠 by improving the hardware usage.…”

Section: Future Workmentioning

confidence: 99%

Non-iterative SDC modulo scheduling for high-level synthesis

Rosa

Bouganis

Bonato

2021

Microprocessors and Microsystems

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“…We assign every sample s an insertion time I s modulo M . For our motivating example in Table I where II = 5 3 , we would have I 0 = 0, I 1 = 2, and I 2 = 4. This means that for all n ≥ 0, we have sample 3n inserted at cycle 5n, sample 3n + 1 inserted at cycle 5n + 2, and sample 3n + 2 inserted at cycle 5n + 4.…”

Section: Sequential Sample Insertionmentioning

confidence: 99%

“…A hardware implementation using this smaller, rational II would show significant speedup, since throughput is the reciprocal of the II. Additionally, recent work has shown that only a very small and sparsely distributed number of hardware/throughput trade offs are possible using integer-II modulo scheduling [5]. Adding implementations that can only be found using rational-II modulo scheduling provides more fine-grained control over the design space.…”

Section: Introductionmentioning

confidence: 99%

Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design

Sittel

Wickerson

Kuimm

et al. 2020

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)

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In modulo scheduling, the number of clock cycles between successive inputs (the initiation interval, II) is traditionally an integer, but in this paper, we explore the benefits of allowing it to be a rational number. This rational II can be interpreted as the average number of clock cycles between successive inputs. As the minimum rational II can be less than the minimum integer II, this translates to higher throughput. We formulate rational-II modulo scheduling as an integer linear programming (ILP) problem that is able to find latency-optimal schedules for a fixed rational II. We have applied our scheduler to a standard benchmark of hardware designs, and our results demonstrate a significant speedup compared to state-of-the-art integer-II and rational-II formulations.

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Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling

Cited by 10 publications

References 13 publications

Integrating Energy-Optimizing Scheduling of Moldable Streaming Tasks with Design Space Exploration for Multiple Core Types on Configurable Platforms

Integrating Energy-Optimizing Scheduling of Moldable Streaming Tasks with Design Space Exploration for Multiple Core Types on Configurable Platforms

Non-iterative SDC modulo scheduling for high-level synthesis

Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design

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