Design strategies for multi-channel low-noise recording systems

Abstract

Parallel recording of micro-scale signals using an integrated system approach has become feasible with recent advances in technology. Practical applications include the recording of neural-signals in a brain-computer interface or in prosthetic implants. In an integrated circuit implementation the restriction in size and available power pose considerable challenges, especially in implanted devices. Furthermore, the provision of both high gain and excellent noise performance in the presence of input offset voltages are mandatory. The presented tutorial highlights design strategies for recording system optimization and compares the performance of actual system implementations with the best-case performance achievable in theory. Special consideration is given to the noise vs. power and offset-tolerance vs. noise trade-offs. An application dependent design strategy is proposed.

Double-Differential Recording and AGC Using Microcontrolled Variable Gain ASIC

“…The power consumption is simulated as 1.2 W ( V supply) and 2 W ( V supply). In the current setup the amplifier power remains negligible compared to the power consumed by the microcontroller of about 300 W. The estimated input-referred spot-noise density is 157 nV/ Hz, on an order comparable with recent low-power designs [22], [23].…”

“…It trades off with lower input impedance in the range of 100 k , decreasing the effective resistance . In applications that require higher input impedance MOSFET transistors may be used but with potentially higher noise levels [23]. The integrator consists of a differential amplifier with feedback capacitors [24].…”

Noise Efficient Integrated Amplifier Designs for Biomedical Applications

“…Although the required amplifier bandwidth varies for different biomedical applications, low-frequency operation not exceeding a few tens of kilohertz is a typical specification [20][21][22]. Generally, the preamplifier determines the signal-to-noise-ratio (SNR) of the signal processing chain [23]. Noise entering after the initial signal amplification becomes less detrimental.…”

“…Reliable suppression of electrode offset voltages before amplification becomes essential to maintain appropriate dynamic range, and it presents a major design challenge. The review presented in [23] indicates that it is not uncommon to spend over 30% of the total power budget on pre-amplification to meet the tight noise requirements. The power budget is ultimately limited by the resulting heat generation, which must not cause any tissue damage.…”

“…The values are further supported by data from an extensive review of publications presented in Section 3. A CMOS input stage provides a good trade-off between high input impedance, high gain, low power consumption, and reasonable manufacturing costs [23]. However, the noise of a MOS field-effect transistor is dominated at low frequencies by its high intrinsic flicker noise.…”