Design Strategy Of Mlscr Devices For Sub-micron Cmos Technology

Lu, Tianbo; Guo, Jung-Yi; Wang, T.; Shone, F.

doi:10.1109/vtsa.1997.614767

Cited by 7 publications

(7 citation statements)

References 5 publications

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“…Now many improved SCR devices with better performance are being researched to replace traditional SCR devices. An improved basic structure is the modified lateral siliconcontrolled rectifier (MLSCR), which introduces heavily doping N+ or P+ regions at the NW/PW interface to reduce the trigger voltage [11]. Based on MLSCR structure, an effective way to reduce the trigger voltage is the MLSCR embedded a PESD region in [12], and the trigger voltage can reach a minimum of 7 V, but it is not low enough for low voltage applications.…”

Section: Introductionmentioning

confidence: 99%

A novel low trigger voltage low leakage SCR for low-voltage ESD protection

Liu,

Yang,

Liu

2024

Semicond. Sci. Technol.

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Reducing trigger voltage has always been a research hotspot in low-voltage electrostatic discharge (ESD) protection applications for integrated circuit. Thus, a novel low trigger voltage low leakage silicon-controlled rectifier (LTVLLSCR) for low-voltage ESD protection has been proposed. The proposed device uses a PMOS connected with the SCR to reduce the trigger voltage and the PMOS gate can be applied with the supply voltage to further reduce the trigger voltage and the leakage current. The operating principle and the physical mechanism of the proposed device were discussed by the Human Body Model simulation. The ESD characteristics of the proposed device were verified in 55 nm CMOS process. The experimental results demonstrate that the trigger voltage of the proposed device can reach a minimum of 2.86 V with an external bias, and the leakage current at 25 ℃ is about 1 nA which can be reduced by 13% with an external bias. With lower trigger voltage, lower leakage, smaller ESD design window and good ESD robustness, the LTVLLSCR is very suitable for 1 V low voltage applications.

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Section: Introductionmentioning

confidence: 99%

A novel low trigger voltage low leakage SCR for low-voltage ESD protection

Liu,

Yang,

Liu

2024

Semicond. Sci. Technol.

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“…However, the conventional LSCR shows a deep snap-back in its I-V characteristic, which violates the ESD design window of most IC processes. Improved designs have been constantly proposed to enable SCR structure to be applied in practical projects [ 5 , 6 ], such as the modified lateral SCR (MLSCR) [ 7 , 8 ] and the diodes-string-triggered SCR (DTSCR) [ 9 , 10 , 11 , 12 , 13 , 14 ]. As such, the DTSCR is particularly well-suited for lower voltage domain with benefit from its lower and adjustable trigger voltage [ 9 ].…”

Section: Introductionmentioning

confidence: 99%

MOSs-String-Triggered Silicon-Controlled Rectifier (MTSCR) ESD Protection Device for 1.8 V Application

et al. 2023

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In this work, a new low voltage-triggered silicon-controlled rectifier named MTSCR is realized in a 65 nm CMOS process for low voltage-integrated circuits electrostatic discharge (ESD) protections. The MTSCR incorporates an external NMOSs-string, which drives the internal NMOS (INMOS) of MTSCR to turn on, and then the INMOS drive SCR structure to turn on. Compared with the existing low trigger voltage (Vt1) ESD component named diodes-string-triggered SCR (DTSCR), the MTSCR can realize the same low Vt1 characteristic but less area penalty of ~44.3% reduction. The results of the transmission line pulsing (TLP) measurement shows that the MTSCR possesses above 2.42 V holding voltage (Vh) and a low Vt1 of ~5.03 V, making it very suitable for the ESD protections for 1.8 V input/output (I/O) ports in CMOS technologies.

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“…But the SCR typically has a high trigger voltage (V t1 ) which exceeds the gate oxide breakdown voltage of the input stage in nanoscale CMOS technology. To reduce the V t1 of SCR, the modified lateral SCR (MLSCR) was reported for input ESD protection by inserting heavily doped n + or p + regions across the boundary of n-well and p-well [3,4]. But the trigger voltage of the MLSCR is still greater than the breakdown voltages of output transistors in the CMOS output buffer.…”

Section: Introductionmentioning

confidence: 99%

Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process

et al. 2020

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Low-voltage-triggered silicon-controlled rectifier (LVTSCR) is expected to provide an electrostatic discharge (ESD) protection for a low-voltage integrated circuit. However, it is normally vulnerable to the latch-up effect due to its extremely low holding voltage. In this paper, a novel LVTSCR embedded with an extra p-type MOSFET called EP-LVTSCR has been proposed and verified in a 28-nm CMOS technology. The proposed device possesses a lower trigger voltage of ~ 6.2 V and a significantly higher holding voltage of ~ 5.5 V with only 23% degradation of the failure current under the transmission line pulse test. It is also shown that the EP-LVTSCR operates with a lower turn-on resistance of ~ 1.8 Ω as well as a reliable leakage current of ~ 1.8 nA measured at 3.63 V, making it suitable for ESD protections in 2.5 V/3.3 V CMOS processes. Moreover, the triggering mechanism and conduction characteristics of the proposed device were explored and demonstrated with TCAD simulation.

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Design Strategy Of Mlscr Devices For Sub-micron Cmos Technology

Cited by 7 publications

References 5 publications

A novel low trigger voltage low leakage SCR for low-voltage ESD protection

A novel low trigger voltage low leakage SCR for low-voltage ESD protection

MOSs-String-Triggered Silicon-Controlled Rectifier (MTSCR) ESD Protection Device for 1.8 V Application

Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process

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