Design techniques for variability mitigation

Abstract

Abstract:As the fabrication technology migrated towards the nanometre scale, 22 nm and beyond, yield enhancement has become one of the challenges facing the integrated circuits design community. Delay and power consumption of the manufactured chips deviate from their predesigned values due to process, voltage and temperature (PVT) variations. This deviation can lead to a considerable loss in yield and reliability. In this paper, we classify and survey the approaches developed to mitigate the PVT variations on the circuit and architectural levels.