Design techniques to combat process, temperature and supply variations in Bluetooth RFIC

Tee, Y.T.; Seng, Yeoh Hoe; Boon, L.P.; Hung, Tsai-Pi; Tachi, S.; Ling, Koh Soo; Murakami, Takeshi; Hui, Shien; Tiong, L.C.; Choon, T.L.; Kheng, W.W.; Jun, Xiang; Li, Meng; Hwi, L.S.; Wei, Xiaoyun; Itoh, M.

doi:10.1109/rfic.2003.1214006

Cited by 6 publications

(1 citation statement)

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“…To suppress the variations, proportional to absolute temperature (PTAT) bias circuit is needed. The temperature variations are compensated using temperature‐independent biasing circuits that provide a nearly constant voltage, current, or transconductance (gm) within the specified temperature range [1, 2]. The low‐voltage design of the PTAT current generation loop is limited by the common‐collector structure of the parasitic vertical bipolar junction transistor (BJT) [3].…”

Section: Introductionmentioning

confidence: 99%

A novel bias circuit with temperature and process compensation for RFIC

Lee

Kim²,

Shin³

et al. 2012

Micro & Optical Tech Letters

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Temperature and process variations have become key issues in design of integrated circuits using deep submicron technologies.In the RF front‐end circuitry, these characteristics must be compensated to maintain acceptable performance across all process corners and throughout the temperature variations. This article proposes a new bias circuit technique to compensate the variations by adding a single NMOS to the normally bias circuit. A 2.4GHz and 5.2GHz LNAs with the proposed bias circuit have the power gain variation (S21) of only 0.3 dB for the −40 to 85°C temperature range in a 65nm RF CMOS process. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2694–2697, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27170

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Section: Introductionmentioning

confidence: 99%