Design technology for fault-free and maximally-parallel wavelength-routed optical networks-on-chip

Abstract

The recent interest in emerging interconnect technologies is bringing the issue of a proper EDA support for them to the forefront, so to tackle the design complexity. A relevant case study is provided by wavelength-routed optical NoCs (WRONoCs), which add communication performance guarantees to the typical latency, throughput and power benefits of an optical link, thus providing an appealing technology for the photonic integration of high-end embedded systems. Typically, only abstract WRONoC models are considered to figure out architecture-level performance, and logic connectivity patterns for the quantification of the required signal strength (i.e., static power). However, this design practice overlooks the needed refinement step, where key physical parameters are assigned such as wavelengths of the optical channels, and size of the optical filters. This step is unfortunately not decoupled from the architectural evaluation, since its main constraint (i.e., avoiding routing faults) turns out to be a key limiter for both the network scale and the achievable communication parallelism. By proposing a formal methodology to select WRONoC parameters while avoding the routing fault concern, this paper aims at maximizing the levels of connectivity and/or of bit parallelism that WRONoCs can achieve, while relating their upper bounds to the uncertainty of the manufacturing process

Logic programming approaches for routing fault-free and maximally parallel wavelength-routed optical networks-on-chip (Application paper)

“…In the experimental campaign in (Peano et al 2016), the focus was computing the maximum obtainable parallelism varying the fabrication parameters, including the possible deviations of the laser wavelengths and the radius imprecisions during fabrication of the device. In this work, instead, we report the timing results of the ASP formulation and of a MILP model.…”

“…We presented two problems arising in the industry of opto-electronic components, in particular in Wavelength-Routed Optical Network on Chip (WRONoC) design. The first problem, published in (Peano et al 2016) arose because in the electronic research the maximal communication parallelism obtainable with a WRONoC was unknown. The problem was solved with an ASP program, that was mentioned, but not described in detail, in (Peano et al 2016).…”

“…The first problem, published in (Peano et al 2016) arose because in the electronic research the maximal communication parallelism obtainable with a WRONoC was unknown. The problem was solved with an ASP program, that was mentioned, but not described in detail, in (Peano et al 2016). We described the ASP program and compared experimentally its performance with a Mixed-Integer Linear Programming (MILP) approach.…”

“…In previous work (Peano et al 2016), we discussed the electronics and photonics design issues linked to the maximization of the parallelism in WRONoCs. As explained in that paper, the optimal design was found using Answer Set Programming (ASP), a technology still not very well known in that research area.…”

OPERON: Optical-electrical Power-efficient Route Synthesis for On-chip Signals

“…Besides, optical NoCs were also designed to enhance its resilience to physical variations, such as environmental temperature and manufacturing instability [4,6]. To increase the potential bandwidth, communication parallelism was emphasized in [7] through a formal methodology. Very recently, with the proposal of LED-driven wires, an automatic place-and-route flow enabled the replacement of electrical wires with on-chip laser sources [8].…”