Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology

Pangracious, Vinod; Mehrez, Habib; Marakchi, Zied

doi:10.1109/3dic.2013.6702342

Cited by 6 publications

(2 citation statements)

References 23 publications

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“…The Tezzaron 3D technology produces small TSVs which are approximately 1.2µm wide with 2.5µm minimum pitch and 6µm height. The estimated TSV delay is ≈ 28pS [17].…”

Section: Timing Modelmentioning

confidence: 99%

Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation

Chtourou

Abid

Pangracious

et al. 2014

2014 International 3D Systems Integration Conference (3DIC)

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International audienceIn this study, we propose a three-dimensional (3D) interconnect network implementation based on a modified Mesh-of-Clusters (MoC) topology for FPGA architecture design. Design and experimental setup is developed to demonstrate the improvement in performance, power and area of 2.5D and 3D MoC-based FPGA architecture. MoC starts with a mesh of nodes and builds a separate hierarchical network along each row and column in the mesh. To obtain the optimal MoC programmable interconnect structure with high performance and density, the routing architecture of the 2D MoC-based FPGA is modified to include long routing segments which span multiple switch blocks in every row and column. By adjusting the percentage of long wire and span, we can design and build 2.5D and 3D high density MoC FPGAs. To design 3D MoC-based FPGAs, we cut the 2D MoC FPGA into two equal FPGA dies and we adjust the long wire span factor to connect the two dies. Then, these long wire segments are converted as 3D through silicon via (TSV) technology. To design 2.5D interposer based multi-FPGA architecture, we use the same principle of cuts and we adjust the long wires span to remain within die connections. However, we apply constraints at cutline location to reduce the die to die interposer connections. A 3D physical design CAD for MoC-based FPGA is developed using Global Foundries 130nm technology node modified to use TSV designs from Tezzaron Semiconductor inc. Using our 3D design and simulation tool flow developed for MoC-based FPGA, we demonstrate that the speed, power and area of 3D MoC-based FPGA architecture are improved respectively by 35%, 21% and 47% in comparison to 2D MoC-based FPGA

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“…The Tezzaron 3D technology produces small TSVs which are approximately 1.2µm wide with 2.5µm minimum pitch and 6µm height. The estimated TSV delay is ≈ 28pS [17].…”

Section: Timing Modelmentioning

confidence: 99%

Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation

Chtourou

Abid

Pangracious

et al. 2014

2014 International 3D Systems Integration Conference (3DIC)

Self Cite

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“…Authors of [6] and [15] studied the design of switch box topology in 3D FPGAs based on the fact that the number of TSVs is limited in 3D ICs. Pangracious et al [14] proposed to use tree-based interconnect topology to build 3D FPGAs in order to reduce the area overhead and improve logic density. Instead of waferstacked 3D FPGAs, people also studied monolithic 3D FP-GAs [12,11] which, according to the results, have better performance.…”

Section: Introductionmentioning

confidence: 99%

Physical Design of 3D FPGAs Embedded with Micro-channel-based Fluidic Cooling

Yang

Srivastava

2016

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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Through Silicon Via (TSV) based 3D integration technology is a promising technology to increase the performance of FP-GAs by achieving shorter global wire-length and higher logic density. However, 3D FPGAs also suffer from severe thermal problems due to the increase in power density and thermal resistance. Moreover, past work has shown that leakage power can account for 40% of the total power at current technology nodes and leakage power increases non-linearly with temperature. This intensifies the thermal problem in 3D FPGAs and more aggressive cooling methods such as micro-channel based fluidic cooling are required to fully exploit their benefits. The interaction between micro-channel heat sink design and the performance of a 3D FPGA is very complicated and a comprehensive approach is required to identify the optimal design of 3D FPGAs subject to thermoelectrical constraints. In this work, we propose an analysis framework for 3D FPGAs embedded with micro-channelbased fluidic cooling to study the impact of channel density on cooling and performance. According to our simulation results, we provide guidelines for designing 3D FPGAs embedded with micro-channel cooling and identify the optimal design for each benchmark. Compared to naive 3D FPGA designs which use fixed thermal heat sink, the optimal design identified using our framework can improve the operating frequency and energy efficiency by up to 80.3% and 124.0%.

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Design of advanced 2D and 3D FPGAs: Architecture-level exploration and algorithm-level optimization

Chtourou

Abid

Marrakchi³

et al. 2016

2016 11th International Design &Amp; Test Symposium (IDT)

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Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology

Cited by 6 publications

References 23 publications

Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation

Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation

Physical Design of 3D FPGAs Embedded with Micro-channel-based Fluidic Cooling

Design of advanced 2D and 3D FPGAs: Architecture-level exploration and algorithm-level optimization

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