Designing a Novel Power Efficient D- Flip-Flop using Forced Stack Technique

Abstract

In Integrated circuits a gargantuan portion of on chip power is expended by clocking systems, which comprises of timing elements such as flip-flops, latches and clock distribution network. These elements absorb approximately 30% to 60% of the total power dissipation in the system. In order to design high performance and power efficient circuits a scrupulous approach should be adopted to reduce the power consumed by flip-flops and latches. In this paper various power efficient flip-flops with low power clock distribution network are examined. Among these flips-flops low Power Clocked Pass Transistor Flip-Flop (LCPTFF) consumes least power than Clocked Pair Shared Flip-Flop (CPSFF), Conditional Data Mapping Flip-Flop and Conditional Discharge Flip-Flop (CDFF). We propose a novel Low Power Forced Stack Clocked Pass Transistor Flip-Flop (LP-FSCPTFF) which reduces the power consumption by approximately 30.1% to 83.93% at 500MHz and 25.5% to 90.1% at 750MHz as compared to original LCPTFF. The simulation is carried out on Tanner EDA v13.0 at 90nm on different voltages at 500MHz and 750MHz. The temperature variation of different flip-flops is also shown at 5 °C, 2 5 °C and 50 °C.

A Novel High Performance Low Power Universal Gate Implementation in Subthreshold Region

“…Another approach by which we can reduce the power due to leakage is by employing forced stack [10] technique, in which an existing transistor is broken down into two transistors half the size of the actual one and this effect is known as the stack effect. Now when implemented in a circuit, these two half size transistors when goes into a cut-off state a reverse bias is induced between the two which culminate in reducing the subthreshold leakage current.…”