Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library

Blotti, A.; Castellucci, Maurizio; Saletti, Roberto

doi:10.1007/3-540-45716-x_13

Cited by 7 publications

(3 citation statements)

References 13 publications

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“…There are different types into which power dissipation can be categorized [2]: 1) Static dissipation since there are leakage currents in the device, 2) Dynamic capacitive power owing to charge and discharge of device load capacitances, and 3) Shortcircuit power dissipation, which happens because of the short circuit currents arising in CMOS. In [3][4][5][6][7][8][9], several adiabatic technologies have been reported. A combination of ECRL with a technique that diminishes gate leakage, simultaneously saving the correct logic state, known as the Sleepy Keeper approach, was implemented in [10,11].…”

Section: Introductionmentioning

confidence: 99%

Energy Conservation of Adiabatic ECRL-Based Kogge-Stone Adder Circuits for FFT Applications

Dhilipkumar¹,

Mohanbabu²

2022

Intelligent Automation &Amp; Soft Computing

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Low Power circuits play a significant role in designing large-scale devices with high energy and power consumption. Adiabatic circuits are one such energy-saving circuits that utilize reversible power. Several methodologies used previously infer the use of CMOS circuits for reducing power dissipation in logic circuits. However, CMOS devices hardly manage in maintaining their performance when it comes to fast switching networks. Adiabatic technology is employed to overcome these difficulties, which can further scale down the dissipation of power by charging and discharging. An Efficient Charge Recovery Logic (ECRL) based adiabatic technology is used here to evaluate arithmetic operations in circuits like inverter, full adder, Carry Look-Ahead adder etc. A better chance at reducing delay in digital circuits is illustrated by developing a Kogge-stone Adder, built using the ECRL technology. The developed circuitry is further integrated into a Fast Fourier Transform (FFT), which demonstrates the circuit's enhancement into DSP applications. Not only does this design reduce delay in VLSI switching circuits, but also narrows the power dissipation down to a minimum. This technique proved superior to the existing PFAL technique by demonstrating almost 10% less power dissipation with minimal propagation delay. All the circuits have been simulated at 45 nm technology using the Tanner EDA tool.

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Section: Introductionmentioning

confidence: 99%

Energy Conservation of Adiabatic ECRL-Based Kogge-Stone Adder Circuits for FFT Applications

Dhilipkumar¹,

Mohanbabu²

2022

Intelligent Automation &Amp; Soft Computing

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“…Such part of the total power dissipated by a circuit is called dynamic power. In order to reduce the dynamic power, an alternative approach to the traditional techniques of power consumption reduction, named adiabatic switching [1][2] [14] [18], has been proposed in the last years. In such approach, the process of charging and discharging the node capacitances is carried out in a way so that a small amount of energy is wasted and a recovery of the energy stored on the capacitors is achieved.…”

Section: Introductionmentioning

confidence: 99%

“…In literature, various kinds of adiabatic circuits proposed [1] [12] [18][20] all of them can be grouped into two fundamental classes: fully adiabatic circuits and quasi-adiabatic or partial energy recovery circuits [1].In the first class, in particular working conditions can consume asymptotically zero energy for operation, the large area occupation and the design complexity make these circuits not competitive with traditional CMOS where as in second class circuits designed to recover large portion of the energy stored in the circuit node capacitances. This energy loss drawback however allows a good trade-off between circuit complexity and then area occupation.…”

Section: Introductionmentioning

confidence: 99%

Power Comparison of CMOS and Adiabatic Full Adder Circuits

Reddy¹,

Prasad²

2011

VLSICS

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Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.

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