Designing Chip-Level Nanophotonic Interconnection Networks

Batten, Christopher; Joshi, Ajay; Stojanović, Vladimir; Asanović, Krste

doi:10.1109/jetcas.2012.2193932

Cited by 61 publications

(9 citation statements)

References 44 publications

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“…The transmission of optical signals through nanophotonic waveguides can provide broadcast [21,23,46,47]. Nanophotonics has been proposed for a variety of network architectures [6,42]. Some proposals use it for onchip broadcast [21,23,46].…”

Section: Related Workmentioning

confidence: 99%

“…Other Technologies. There are two emerging technologies that can also offer on-chip broadcast capabilities: transmission lines (TLs) [4,5,10,33,34,41,43] and nanophotonics [6,21,23,42,46,47]. While these technologies are more energy-efficient and provide more bandwidth than wireless communication, they are more complicated and less scalable than wireless communication.…”

Section: Introductionmentioning

confidence: 99%

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WiSync

Abadal

Cabellos‐Aparicio

Alarcón

et al. 2016

SIGARCH Comput. Archit. News

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In shared-memory multiprocessing, fine-grain synchronization is challenging because it requires frequent communication. As technology scaling delivers larger manycore chips, such pattern is expected to remain costly to support.In this paper, we propose to address this challenge by using on-chip wireless communication. Each core has a transceiver and an antenna to communicate with all the other cores. This environment supports very low latency global communication. Our architecture, called WiSync, uses a per-core Broadcast Memory (BM). When a core writes to its BM, all the other 100+ BMs get updated in less than 10 processor cycles. We also use a second wireless channel with cheaper transfers to execute barriers efficiently. WiSync supports multiprogramming, virtual memory, and context switching. Our evaluation with simulations of 128threaded kernels and 64-threaded applications shows that WiSync speeds-up synchronization substantially. Compared to using advanced conventional synchronization, WiSync attains an average speedup of nearly one order of magnitude for the kernels, and 1.12 for PARSEC and SPLASH-2.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

WiSync

Abadal

Cabellos‐Aparicio

Alarcón

et al. 2016

SIGARCH Comput. Archit. News

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“…Binkert et al (2011) and Polatis (2016) Without the limitation of port bandwidth, the power consumption of optical switch (384 ports) is just 100 W which is more than ten times reduction in power of each port than electronic switch. Although there have been extensive researches on silicon-photon on-chip network for processor design (Batten et al 2013;Ahn et al 2009;Pan et al 2009;Vantrease et al 2008;Beausoleil et al 2008), how to design an optical interconnection network for the next generation of supercomputer system has not been actively explored to embrace the emerging technology.…”

Section: Introductionmentioning

confidence: 99%

Wormhole optical network: a new architecture to solve long diameter problem in exascale computer

et al. 2019

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The exascale computer will be built in the near future thanks to rapid innovations in semiconductor logic, memory, architectures, interconnections and other essential technologies. It is difficult to design an interconnection network that combines high performance with low power consumption. Therefore, building an interconnection network with high cost performance plays a critical role in building such a large scale system. Currently, torus-interconnected network like 6D-Torus possesses suitable properties for the petascale computer. However, the diameter within the torus-interconnected network is too long to achieve efficient global communication in the exascale computer. In addition, a direct connection method is not adaptive to the diverse characteristics of traffic. Here, we propose an architecture called Wormhole Optical Network (WON) for the exascale computer which is based on optical circuit switching. WON was designed to fully integrate into the electrical network of 6D-Torus. WON allows for the use of three novel technologies, namely the dynamic topology with optical links, algorithm of cross dimension order routing, and strategy of flow control for deadlock-free. We evaluated WON using both a prototype system and a simulator for the exascale computer. Our analysis shows that compared to the traditional electrical architecture, WON architecture reduced the time of data communication by 14-29% on exascale, a result obtained for a wide selection of diverse applications. Through enabling an SDN controller to adjust topology, WON maintains high utilization of optical links for inter-process communication from diverse applications. Further, we quantified WON's flexibility of job deployment for mitigating hotspot traffic. We show that WON reduced latency by 20-35% in the large-range deployment and improved throughput by 30% in the long-distance deployment.

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“…As reported in [3], NoC switching activity accounts for over 50% of the interconnect power consumption. NoC efficiency thus needs to be further improved in order to efficiently interconnect systems with still increasing number of cores and required bandwidth density [4].…”

Section: Introductionmentioning

confidence: 99%

Offline Optimization of Wavelength Allocation and Laser Power in Nanophotonic Interconnects

Luo

Killian

Beux

et al. 2018

J. Emerg. Technol. Comput. Syst.

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Optical Network-on-Chip (ONoC) is a promising communication medium for large-scale Multiprocessor System on Chip (MPSoC). Indeed ONoC can outperform classical electrical NoC in terms of energy efficiency and bandwidth density, in particular, because this medium can support multiple transactions at the same time on different wavelengths by using Wavelength Division Multiplexing (WDM). However, multiple signals sharing simultaneously the same part of a waveguide can lead to inter-channel crosstalk noise. This problem impacts the Signal to Noise Ratio (SNR) of the optical signals, which leads to an increase in the Bit Error Rate (BER) at the receiver side. If a specific BER is targeted, an increase of laser power should be necessary to satisfy the SNR. In this context, an important issue is to evaluate the laser power needed to satisfy the various desired communication bandwidths based on the BER performance requirements. In this paper, we propose an off-line approach that concurrently optimizes the laser power scaling and execution time of a global application. A set of different levels of power is introduced for each laser, to ensure that optical signal can be emitted with just-enough power to ensure targeted BER. As result, most promising solutions are highlighted for mapping a defined application onto 16-core ring-based WDM ONoC.

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Designing Chip-Level Nanophotonic Interconnection Networks

Cited by 61 publications

References 44 publications

WiSync

WiSync

Wormhole optical network: a new architecture to solve long diameter problem in exascale computer

Offline Optimization of Wavelength Allocation and Laser Power in Nanophotonic Interconnects

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