Designing Data Structures to Minimize Bit Flips on NVM

Abstract

The advent of byte-addressable non-volatile memory technologies such as phase change memory (PCM) has spurred a flurry of research on topics including consistency and durability of data structures across power failures and optimizing systems for the low-latency nature of these technologies, while typically aiming to increase lifetime and reduce power consumption by reducing the number of writes to the non-volatile memory. However, in technologies such as PCM, it is bit flips that consume power and wear out cells, not writes. Thus, PCM controllers do not rewrite cells unless the cell changes value. However, this crucial optimization, reducing the number of bits flipped, has not been sufficiently explored for the rest of the hardware and software stack. We develop a framework for using the number of bit flips as the measure of "goodness" for a range of hardware and software techniques. We also introduce several simple and straightforward modifications to existing data structures that can reduce the number of bit flips over time, and profile use cases in which the approach with the fewest writes does not also minimize bit flips. Based on these findings, we discuss potential approaches that can further minimize bit flips, better optimizing hardware and software for non-volatile memory technologies such as PCM.

Relieving Compression-Induced Local Wear on Non-Volatile Memory Block via Sliding Writes

“…There are also existing works that reduce bit flips for specific applications. Bittman et al [ 37 ] made improvements to the hash list length, key-value and mapping method, and XOR the link list to reduce bit flips. Bittman et al [ 13 ] used the XOR to turn the same part into 0, thus reducing bit flips.…”