Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation

Quadri, Imran Rafiq; Meftali, Samy; Dekeyser, Jean-Luc

doi:10.1109/dasip.2010.5706248

Cited by 10 publications

(8 citation statements)

References 13 publications

(16 reference statements)

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“…Reconfigurable systems' modeling is treated by several researchers and teams (Rafiq Quadri et al, 2009), (Rafiq Quadri et al, 2010), (Quadri et al, 2010), (Vidal et al, 2010), (Vidal et al, 2011). A recent project called FAMOUS (Famous Project, ) is interested in this topic and involves many partners from research and industry.…”

Section: Hardware Level Adaptation Modelingmentioning

confidence: 99%

High Level Design of Adaptive Real-time Embedded Systems - A Survey

Said¹,

Kacem²,

Amor³

et al. 2013

Proceedings of the 1st International Conference on Model-Driven Engineering and Software Development

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Real time embedded systems (RTES) know a growing complexity due to modern applications requirements and architectures complexity especially with the addition of the multiprocessor feature. They are equally subject to a variety of constraints due to their mobility. They need to react to environment variability, resource limitations and timing constraints. An emergent solution to deal with this complexity is the integration of adaptation strategies in embedded systems design flow. The design space of multi-layer adaptation decisions is becoming increasingly vast and difficult to explore. Development of such systems at low system levels is therefore increasingly tedious especially with the limitations of computer aided design tools. Using MDE approach and the UML/MARTE profile for high abstraction level design is becoming a promising solution to ease the design of RTES. In the present paper we recall and classify existing works built around adaptive embedded systems. We concentrate on a set of criteria to help highlighting the shortages of existing approaches on modern adaptive RTES design. We focus on the design environment, adaptation features, online time constraints verification and performance assessment. Finally, we present our future works to cope with the limits of existing solutions while taking into account the observed criteria.

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Section: Hardware Level Adaptation Modelingmentioning

confidence: 99%

High Level Design of Adaptive Real-time Embedded Systems - A Survey

Said¹,

Kacem²,

Amor³

et al. 2013

Proceedings of the 1st International Conference on Model-Driven Engineering and Software Development

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“…The approach requires a strong level of expertise as all elements of the DPR design flow need to be modelled. Despite its complexity, in [21] the authors demonstrate how their methodology can be exploited to move from MARTE models to automatic code generation. They make use of the so-called Deployment Meta-model [22], which in fact provides several mechanisms to link low-level implementation (e.g.…”

Section: Hardware Resource Modeling With Uml Profilesmentioning

confidence: 99%

A high-level methodology for automatically generating dynamic partially reconfigurable systems using IP-XACT and the UML MARTE profile

Ochoa-Ruiz¹,

Labbani²,

Bourennane³

et al. 2012

Des Autom Embed Syst

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Dynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building complex systems remains a daunting task. Recently, approaches based on Model-Driven Engineering (MDE) and UML MARTE standard have emerged which aim to simplify the design of complex SoCs, and in some cases, DPR systems. Nevertheless, many of these approaches lacked a standard intermediate representation to pass from high-levels of descriptions to executable models. However, with the recent standardization of the IP-XACT specification, there is an increasing interest to use it in MDE methodologies to ease system integration and to enable design flow automation. In this paper we propose an MARTE/MDE approach which exploits the capabilities of IP-XACT to model and automatically generate DPR SoC designs. We present the MARTE modeling concepts and how these models are mapped to IP-XACT objects; the emphasis is given to the generation of IP cores that can be used in the Xilinx EDK (Embedded Design Kit) environment, since we aim to develop a complete flow around their Dynamic Partial Reconfiguration design flow. Finally, we present a case study integrating the presented concepts, showing the benefits in design efforts compared with a purely VHDL approach and using solely EDK. Experimental results show a reduction of

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“…Several works have tackled the use of MARTE in SoC design, specifically at the deployment level, such as the MoPCoM [6] and GASPARD [7] frameworks. The main disadvantage is that, as with many other MDE methodologies, both approaches make use of nonstandardized deployment representations.…”

Section: Related Workmentioning

confidence: 99%

“…Several industrial cases studies have demonstrated that the adoption of IP-XACT facilitates the configuration, integration, and verification in multi-vendor SoC and IP integrating design flows [6], [7].…”

Section: Related Workmentioning

confidence: 99%

Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT

Ochoa-Ruiz

Labbani

Bourennane

et al. 2012

2012 23rd IEEE International Symposium on Rapid System Prototyping (RSP)

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-This paper presents a framework which facilitates the parameterization and integration of IP cores into partially reconfigurable SoC platforms, departing from a high-level of abstraction. The approach is based in a Model-Driven Engineering (MDE) methodology, which exploits two widely used standards for Systems-on-Chip specification, MARTE and IP-XACT. The presented work deals with the deployment level of the MDE approach, in which the abstract components of the platform are first linked to the lower level IP-XACT counterparts. At this phase, information for parameterization and integration is readily available, and a synthesizable model can be obtained from the generated IP-XACT through model transformations. We detail how certain IP-XACT objects are exploited in our approach; the emphasis is given to the generation of IP cores in a Xilinx EDK environment. We provide a case study in which a complete DPR platform is modeled in MARTE and implemented in a FPGA.

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Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation

Cited by 10 publications

References 13 publications

High Level Design of Adaptive Real-time Embedded Systems - A Survey

High Level Design of Adaptive Real-time Embedded Systems - A Survey

A high-level methodology for automatically generating dynamic partially reconfigurable systems using IP-XACT and the UML MARTE profile

Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT

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