Designing Fast Fourier Transform Accelerators for Orthogonal Frequency-Division Multiplexing Systems

Versatile digital architecture for mobile terminal

“…Therefore, the final signal is reinforced which leads to performance improvement [13][14][15]. The Fast Fourier Transform (FFT) and its inverse (IFFT) are very important algorithms in the most promising modulation techniques such as the Orthogonal Frequency Division Multiplexing (OFDM) [16,17]. Likewise, the Cordic [18] is a required algorithm for computing values of elementary functions (such as trigonometric and hyperbolic functions) with the desired precision, using only additions, subtractions, digit shifts, comparators and stored constants.…”

“…Moreover, it can achieve high-throughput and has a regular structure and relatively simple control [23,24]. Several pipelined architectures have been developed, such as multi-path delay commutator (MDC) [25], single path delay feedback (SDF) [17,25], and single path delay commutator (SDC). Considering these previous works, the SDF pipeline architecture can be easily scaled and parameterized in hardware design [17,25,26].…”

“…Several pipelined architectures have been developed, such as multi-path delay commutator (MDC) [25], single path delay feedback (SDF) [17,25], and single path delay commutator (SDC). Considering these previous works, the SDF pipeline architecture can be easily scaled and parameterized in hardware design [17,25,26]. Therefore, a pipeline architecture allows to achieve 8-8192-points FFT by adding several processing elements (PE) can be proposed.…”

A Reconfigurable Application-specific Instruction-set Processor for Fast Fourier Transform processing

“…COFFEE controls the cycle accurate processing of the AVATAR-generated accelerator by passing the control words to the control registers of the accelerator. AVATAR is written in VHDL and most of the information related to AVATAR can be found in [13] and [12] but the key points are highlighted here to build the discussion.…”

“…In this paper, we have used a template-based CGRA called AVATAR [13] as the reconfigurable part in ASIP. In past, AVATAR-generated mixed-radix(2, 4) FFT accelerator could process 64 and 128-point of FFT algorithms while satisfying IEEE-802.11n execution time constraints.…”