Designing fault tolerant FSM by nano-PLA

Abstract

The paper deals with designing fault tolerant finite state machines (FSMs) by nanoelectronic programmable logic arrays (PLAs). Two main critical parameters of the fault tolerant nano-PLAs, the area and the number of crosspoint devices, are considered as optimization criteria for the synthesis. The paper introduces a method for synthesizing fault tolerant nano-PLA based FSMs. The method is based on decomposing an initial PLA description of the FSM into a three interacting portions. The proposed solution provides significant reduction of the area without meaningful increasing of a number of crosspoint devices in comparison with known solutions and provides a trade-off between the area and the number of devices in designing FSMs by PLAs.

Design of Moore finite state machine with extended coding space

“…As it is mentioned in [2], successful computation structures return back at the next round of the technological spiral. Now the return of PLA basis can be observed in the hybrid FPGAs [8], as well as in CoolRunner CPLD by Xilinx.…”

“…In the nanoelectronics, these devices are named nano-PLAs. Nowadays, extensive research is conducted in the fields connected with nano-PLAs [2]. In the case of application-specified integrated circuits (ASIC), the combinational logic is very often implemented using so called matrix structures where the principle of distributed logic is used [3].…”

Error detection and correction architecture of finite state machine state transition for nanometer process technology

“…The existing methods [9][10][11][12] detect an error by comparing the original state bits and additional encoded state bits using error detection and a correction code. The use of hamming code in [13] can detect and correct the state transition error.…”

“…If the transition is valid, the transitioned next state is regarded as the correct next state. Like the existing robust FSM architectures [9][10][11][12][13], the proposed scheme assumes that an error occurs at only one sub-block at a time. Since the key bit error is detected and corrected by using the relationship between the present state, the next state, and the parity bit, an assumption should be made that other sub-blocks except the key bit generation block do not have errors in the case of the key bit error.…”

“…A parity-tree selection scheme [11] for concurrent error detection in FSMs is proposed based on compaction of the state and the output bits of an FSM in order to minimize the number of parity trees. An optimal method [12] for synthesizing FT nano-PLA-based FSMs is proposed by considering the optimal criteria for the area and number of crosspoint devices.…”