Designing of Test Pattern Generators for stimulation of crosstalk faults in bus-type connections

Abstract

The paper reveals a completely new and original structure of a Test Pattern Generator (TPG) dedicated for detection of crosstalk faults that may happen to bus-type connections between individual cores of a System on a Chip (SoC). The TPG is designed to generate either the MAFM (Maximum Aggressor Fault Model) sequence of test vectors or the XMAFM (eXtended Maximum Aggressor Fault Model) one, which guarantees that all possible crosstalk faults of the capacitive nature that may occur between individual lines of a digital bus are detectable. The study presents the synthesizable and parameterized (scalable) model of the mentioned TPG developed in the VHDL language. The proposed TPG structures feature with high working frequency and good scalability in terms of both the hardware overhead and length of the output test sequence. In addition, the TPG structure enables easy integration of the solution with Design for Testability solutions, such as a scan path, a wrapper designed in compliance with the IEEE 1500 standard or with the Built-in Self-Test circuits that might be already implemented in IP cores embedded in a SoC. In such a case the area overhead of the proposed structure never exceeds several dozens of equivalent gates, which is a negligible amount.

New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections

“…from 17,6% up to as much as 35,2% than in case of solutions disclosed in other studies [37], [11]. In addition, the maximum frequency for the circuit operation is higher by 2.5% up to 43% than for the circuit disclosed in [9]. Although the MAFM test sequences provided by the TPG of the (2n-1)-SR-TPG type are by as much as 35% longer than the ones reported in [37], for more than one aggressor line they are much shorter than in case of the solution revealed in [28].…”

“…The TPC0 and TPC1 circuits are synchronized by the corresponding rising and falling edges of the clock waveform. The new design of the circuit for counting of test vectors makes it possible to achieve higher rates of the TPG operating frequency as compared to the solution disclosed in [9].…”

“…The Test Pattern Generator of the (2n-1)-SR-TPG type was compared against the 2n-SR-TPG circuit disclosed in [9].…”

“…The TPG disclosed in this study is an improved option of the solution already described in [9]. The new design of the TPG benefits from reduction in length of the shift register and alteration of the test vector counter.…”

“…The new design of the TPG benefits from reduction in length of the shift register and alteration of the test vector counter. These measures made it possible to achieve a TPG structure that highlights with less hardware overhead and much higher operation frequency than the solution presented in [9]. …”