Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems

A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

“…Cache coherence protocols specify the activity of one core on shared cached data as a function of the activity of other cores on the same data. Kaushik et al [128] extends the previous proposal made by Hassan et al [129] focused on a predictable cache coherence protocol based on the use of certain invariants applied to the classic MSI protocol [130]. The proposal made by Kaushik et al [128] focuses on design invariants for the MESI protocol [130] from analysis of the unpredictable behavior of the conventional MESI coherence protocol.…”

“…Finally, approaches have been proposed to deal with the problem of data interference in a system where data is shared by implementing Predictable Cache Coherence Protocols. The predictable MSI (PMSI) protocol proposed by Hassan et al [129] and the cache coherence protocols (PMSI and PMESI) presented by Kaushik et al [128] provide considerable performance improvements, do not impose any scheduling restrictions, and do not require any source-code modifications. On the other hand, implementing these invariants to deal with unpredictable scenarios requires architecture changes and the conventional coherence protocol.…”

“…Predictable cache coherence protocol Description HRT/SRT/AVG [129] Predictable MSI Design invariants to ensure predictability SRT [128] Predictable MESI Design invariants to ensure predictability SRT [135] Discriminative coherence protocol Reduces the coherence delays SRT presented a framework to determine the worst-case response time of a task in a real-time multicore system with the temporal dimension of memory scheduling and dynamic memory bandwidth regulation. A bandwidth partitioning scheme such as MemGuard is used.…”

Predictable Sharing of Last-level Cache Partitions for Multi-core Safety-critical Systems

“…Compared to [7], our analysis provides an exact (non-probabilistic) bound of a memory access in the LLC, and does not rely on MBPTA. Our work assumes that a TDM bus arbitration has one slot in each period, which is common in controlling access to resources in safety-critical systems [1,5]. We also identified the worst-case scenario for the LLC evictions, and that in the worst-case the latency can be unbounded if the arbitration has no constraint.…”

“…This provides temporal isolation to tasks executing on a core from other tasks executing on another core. However, there are multiple downsides to LLC partitioning: (1) it can significantly affect average-case performance, (2) it can lead to underutilization of cache capacity, and (3) prevent coherent data sharing [1]. Downside (1) is a result of each core having a smaller part of the LLC.…”