Designing Robust GALS Circuits with Triple Modular Redundancy

Lechner, Jakob

doi:10.1109/edcc.2012.25

Cited by 4 publications

(2 citation statements)

References 9 publications

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“…It is considered that we have merged the recovery controller unit and the conventional majority voter in our proposed TMR system in order to reduce area overhead and improve time efficiency. According to [29] a significant reduction in area overhead, more than 20 transistors has been omitted, is achieved.…”

Section: Proposed Architecturementioning

confidence: 99%

“…The delay value depends on the duration of the hazard, but using four back‐to‐back inverters is suggested in [39] which is claimed to suppress hazards with durations lower than 0.9 ns. We have reduced the area overhead by omitting the whole recovery controller unit [29] and replacing it with two Muller C‐Elements. Hence, not only the area overhead is reduced in terms of transistor counting, but also the recovery mode has been sped up which improves the circuit’s time efficiency.…”

Section: Proposed Architecturementioning

confidence: 99%

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Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme

Sheikhpur

Taheri

Ansari³

et al. 2021

IET Computers & Digital Tech

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Digital data transmission is day by day more vulnerable to both malicious and natural faults. With an aim to assure reliability, security and privacy in communication, a low-cost fault resilient architecture for Advanced Encryption Standard (AES) is proposed. In order not to degrade the reliability of our AES architecture, the reliability of voter is very important, for which reason we have introduced a novel voting scheme include a majority voter (named TMR voter) and an error barrier element (named DMR voter). In this paper, a reliable and secure 32-bit data-path AES implementation based on our robust fault resilient approach is developed. We illustrate that the proposed architecture can tolerate up to triple-bit (byte) simultaneous faults at each pipeline stage's logic and verify our claim through extensive error simulations. Error simulation results also show that our architecture achieves close to 100% fault-masking capability for multiple-bit (byte) faults. Finally, it is shown that the Application-Specific Integrated Circuit implementation of the fault-tolerant architectures using the composite field-based S-box, CFB-AES, and ROMbased S-box, RB-AES allows better area usage, throughput and fault resilience trade-off compared to their counterparts. So, it provides the most appropriate features to be used in highly-secure resource-constraint applications.

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Section: Proposed Architecturementioning

confidence: 99%

Section: Proposed Architecturementioning

confidence: 99%