Designing the PowerPC 60X bus

Allén, Markus; Alexander, M.; Wright, Chris; Chang, J.

doi:10.1109/mm.1994.363068

Cited by 8 publications

(7 citation statements)

References 1 publication

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“…One good example of this is the bus parking mechanism used in the PowerPC 60x [3]. Here, the bus arbiter speculatively grants a bus master before receiving a master request; this grant message is coordinated by broadcasting to all attached devices.…”

Section: Empirical Wireless Measurementsmentioning

confidence: 99%

Flit

Gummeson

Zhang

Ganesan

2012

Proceedings of the 10th International Conference on Mobile Systems, Applications, and Services

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RFID-scale sensors present a new frontier for distributed sensing. In contrast to existing sensor deployments that rely on battery-powered sensors, RFID-scale sensors rely solely on harvested energy. These devices sense and store data when not in contact with a reader, and use backscatter communication to upload data when a reader is in range. Unlike conventional RFID tags that only transmit identifiers, RFID sensors need to transfer potentially large amounts of data to a reader during each contact event. In this paper, we propose several optimizations to the RFID network stack to support efficient bulk transfer while remaining compatible with existing Gen 2 readers. Our key contribution is the design of a coordinated bulk transfer protocol for RFID-scale sensors that maximizes channel utilization and minimizes energy lost due to idle listening while also minimizing collisions. We present an implementation of the protocol for the Intel WISP, and describe several parameters that are tuned using empirical measurements that characterize the wireless channel. Our results show that the burst protocol improves goodput in comparison to vanilla EPC Gen 2 tags, improves energy-efficiency, allows multiple RFID sensors to share the channel, and also coexists with passive, non-sensor tags.

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Section: Empirical Wireless Measurementsmentioning

confidence: 99%

Flit

Gummeson

Zhang

Ganesan

2012

Proceedings of the 10th International Conference on Mobile Systems, Applications, and Services

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“…The MPC105 bridge chip supports PowerPC 601, 603, and 604 microprocessors 1,2,3 by bridging the peripheral component interconnection device to the 60X bus. 4 With its integrated memory and secondary cache control, the chip enables system designers to rapidly create systems using peripherals already designed for PCI and other standard PC interfaces. The major product goals for our design included supporting the data transfer between the PowerPC processor, memory, and PCI interfaces; providing controls for off-chip secondary cache and memory systems; assuring PowerPC reference platform specification compatibility and system-configuration flexibility; reducing silicon and packaging costs; and optimizing performance.…”

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confidence: 99%

Designing the MPC105 PCI bridge/memory controller

Wang¹,

Bryant²,

Carlson³

et al. 1995

IEEE Micro

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The MPC105 peripheral component interconnection bridge/memory controller provides a platform-specification-compliant bridge between PowerPC microprocessors and the PCI bus. With it, designers can create systems using peripherals already designed for a variety of standard PC interfaces. This bridge chip also integrates a secondary cache controller and high-performance memory controller that supports DRAM or synchronous DRAM and ROM or flash ROM.

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“…Consider the 60X bus [1] used by the PowerPC 604; a cache-line (32-bytes) of data can be transfered in as few as 6 bus cycles compared to 24 bus cycles required for eight uncached 4-Byte transfers 1 . This difference is accentuated in StarT-Voyager by the 4:1 processor clock to bus clock ratio.…”

Section: Design Considerationsmentioning

confidence: 99%

Message passing support on StarT-Voyager

Ang¹,

Chiou²,

Rudolph³

et al.

Proceedings. Fifth International Conference on High Performance Computing (Cat. No. 98EX238)

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No single message passing mechanism can efficiently support all types of communication that commonly occur in most parallel or distributed programs. MIT's StarT-Voyager, a hybrid message passing/shared memory parallel machine, provides four message passing mechanisms to achieve high performance over a wide spectrum of communication types and sizes. Hardware and address translation enforced protection allows direct user-level access to message passing facilities in a multiuser environment. StarT-Voyager's protection scheme improves upon past designs by not requiring strictly synchronized gang-scheduling, and by supporting non-monolithic protection domains. To minimize the development effort and cost, the machine is designed to use unmodified commercial PowerPC 604-based SMP systems as the building block. A Network End-point Subsystem (NES) card which plugs into one of each SMP's processor card slots provides the interface to Arctic, a low-latency, highbandwidth network developed at MIT. This paper describes StarT-Voyager's message passing mechanisms and their predicted performance.

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Designing the PowerPC 60X bus

Cited by 8 publications

References 1 publication

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Designing the MPC105 PCI bridge/memory controller

Message passing support on StarT-Voyager

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