Designs of Level-Sensitive T Flip-Flops and Polar Encoders Based on Two XOR/XNOR Gates

Yan, Aibin; Liu, Z.; Huang, Zhengfeng; Girard, Patrick; Wen, Xiaoqing

doi:10.3390/electronics11101658

Cited by 7 publications

(10 citation statements)

References 35 publications

(141 reference statements)

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“…Additionally, no energy calculations are made for the suggested design. A QTFF is shown in [15] This design has a number of drawbacks, including its large size, the existence of internal nodes, and the absence of an energy calculation.…”

Section: Existing Work On Qtffmentioning

confidence: 99%

“…In addition, the main layout utilizes two MVs: One MV functions as an AND gate, while the other MV functions as an XOR gate. This work is driven by the layouts of [13] and [15]. The processing of input requires five clock zones (1.25-clock cycles).…”

Section: Proposed Designmentioning

confidence: 99%

“…The aim is to demonstrate the unique contributions and advancements made by the proposed QTFF in comparison to previous works. The design of QTFF has been investigated in a number of pertinent studies [9][10][11][12][13][14][15][16], which have already been mentioned in the literature study. The work [14] cannot be compared to the proposed work because it employs a different layout design method and does not use an MV.…”

Section: Comparisonsmentioning

confidence: 99%

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Elementary design and analysis of QCA-based T-flipflop for nanocomputing

Khan

2023

Journal of Electrical Engineering

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This work presents a new T-flipflop design based on quantum-dot cellular automata technology, with the standard two inputs (T and clock) and two outputs (Q and Q̄). It adheres to the typical QCA layout design approach, which consists of two majority voters and one inverter (to produce the complementary output, Q̄). It is a single-layered design with no crossover. A memory loop is used to retain previous values and aid the toggling operation of the T-flipflop. This design achieves improved functionality and reduced area requirement compared to existing designs. In addition, the study investigated energy loss and cost functions. In particular, the total energy loss is reduced by 10% and 22% compared to the best design when analyzed with the QCAPro and QCADesigner-E (QDE) tools, respectively. The area-delay and energy-delay cost functions outperform the best current design by 1.3 and 1.07 times, respectively. Overall, this work advances QCA-based flipflop (QTFF) designs and emphasizes the potential of QCA technology for creating effective QCA circuits.

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Section: Existing Work On Qtffmentioning

confidence: 99%

Section: Proposed Designmentioning

confidence: 99%

Section: Comparisonsmentioning

confidence: 99%

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Elementary design and analysis of QCA-based T-flipflop for nanocomputing

Khan

2023

Journal of Electrical Engineering

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“…However, it uses a lot of cells and has a large area. In addition, a variety of QCA circuits have been proposed, such as: full adders [34,35], memory cell [36][37][38], multi-bit full comparator [39] and other circuits [40][41][42][43][44][45]. Sequential logic elements have also been implemented in these QCA circuits.…”

Section: Introductionmentioning

confidence: 99%

Designs of Array Multipliers with an Optimized Delay in Quantum-Dot Cellular Automata

Yan

Liu

et al. 2023

Electronics

Self Cite

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Quantum-dot cellular automata (QCA) has been considered as a novel nano-electronic technology. With the advantages of low power consumption, high speed, and high integration, QCA has been treated as the potential replacement technology of the CMOS (complementary metal oxide semiconductor) which is currently used in the industry. This paper presents a QCA-based array multiplier with an optimized delay. This type of circuit is the basic building block of many arithmetic logic units and electronic communication systems. Compared to the existing array multipliers, the proposed multipliers have the smallest cell count and area. The proposed designs used a compact clock scheme to reduce the carry delay of the signals. The 2 × 2 array multiplier clock delay was reduced by almost 65% compared to the existing designs. Moreover, since the multiplier exhibits a good scalability, for further proof, we proposed a 3 × 3 array multiplier. Simulation results asserted the feasibility of the proposed multipliers. Extensive comparison results demonstrated that when the design scaling was increased, our proposed designs still displayed an efficient overhead in terms of the delay, cell count, and area. The QCADesigner tool was employed to validate the proposed array multipliers. The QCADesigner-E was used to measure the power dissipation of the alternative compared solutions.

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“…It provides high operational speed/frequency (in the range of THz) [3,4], high device density [5], and low power dissipation [6]. Therefore, QCA is attracting researchers to design various digital circuits, such as adders, multipliers, multiplexers, encoders, decoders, flip flops, shift registers, content addressable memory, etc., in QCA technology to overcome the issues faced by CMOS [7][8][9][10][11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

Design of Cost-Efficient SRAM Cell in Quantum Dot Cellular Automata Technology

et al. 2023

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SRAM or Static Random-Access Memory is the most vital memory technology. SRAM is fast and robust but faces design challenges in nanoscale CMOS such as high leakage, power consumption, and reliability. Quantum-dot Cellular Automata (QCA) is the alternative technology that can be used to address the challenges of conventional SRAM. In this paper, a cost-efficient single layer SRAM cell has been proposed in QCA. The design has 39 cells with a latency of 1.5 clock cycles and achieves an overall improvement in cell count, area, latency, and QCA cost compared to the reported designs. It can therefore be used to design nanoscale memory structures of higher order.

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Designs of Level-Sensitive T Flip-Flops and Polar Encoders Based on Two XOR/XNOR Gates

Cited by 7 publications

References 35 publications

Elementary design and analysis of QCA-based T-flipflop for nanocomputing

Elementary design and analysis of QCA-based T-flipflop for nanocomputing

Designs of Array Multipliers with an Optimized Delay in Quantum-Dot Cellular Automata

Design of Cost-Efficient SRAM Cell in Quantum Dot Cellular Automata Technology

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