Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications

Abstract

Abstract-Asynchronous implementation techniques, which measure logic delays at runtime and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst case delays at design time and constrain the clock cycle accordingly. Desynchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus, permitting widespread adoption of asynchronicity without requiring special design skills or tools. In this paper, different protocols for desynchronization are first studied, and their correctness is formally proven using techniques originally developed for distributed deployment of synchronous language specifications. A taxonomy of existing protocols for asynchronous latch controllers, covering, in particular, the four-phase handshake protocols devised in the literature for micropipelines, is also provided. A new controller that exhibits provably maximal concurrency is then proposed, and the performance of desynchronized circuits is analyzed with respect to the original synchronous optimized implementation. Finally, this paper proves the feasibility and effectiveness of the proposed approach by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architecture.

Current trends in high-level synthesis of asynchronous circuits

“…The de-synchronization method described in [26] may be seen as taking the above ideas one step further in the sense that a synchronous circuit is transformed into a truly asynchronous circuit by substitution of clocked registers by asynchronous handshake-registers. The synchronous circuit is a pure clocked circuit without any of the flow-control or handshaking described above.…”

Elasticity and Petri Nets

“…In [16,17], marked graphs are the underlying formalism to model the flow of data in asynchronous circuits. Signal Transition Graphs [18,19] have also been used to specify asynchronous controllers.…”

Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks

“…Inter-register handshake insertion approach where clock connected to registers is substituted by handshaking between the registers placed at the same points in the circuit (Fig. 1b) is used by NCL [19] and De-synchronization [20] flows.…”

“…We have proved that asynchronous fine-grain pipelined circuit generated by our flow is live, safe and flow-equivalent to original specification (we borrow the notion of flow-equivalence and a method of proof from [20]). Flow-equivalence means that for each stage that corresponds to a latch in RTL implementation, the value stored at the i-th pulse of the control signal is the same as the value stored at the i-th cycle of the synchronous circuit.…”