Desynchronizing Paralleled GaN HEMTs to Reduce Light-Load Switching Loss

Abstract

Parallel connection of GaN high-electron-mobility transistors (HEMTs) is a more cost-effective or even an unavoidable solution to achieve higher current ratings. As the load decreases, however, the switching loss of paralleled HEMTs becomes dominant over the conduction loss, and the overall power conversion efficiency drops sharply. To reduce the light-load switching loss, this paper proposes a desynchronizable paralleling scheme. The midpoint (AC terminal) of each paralleled HEMT half bridge is connected with a commutation inductor, which thus, enables two operation modes: synchronous and asynchronous modes. The synchronous mode is activated at heavy loads to share the high current; the added commutation inductors lead to better current sharing than the direct parallel. When operating at light loads, however, the paralleled devices are desynchronized to generate a circulating current flowing through the commutation inductors. The circulating current enables the lagging HEMTs to achieve the zero-voltage switching (ZVS) and allows the leading ones to turn on at a current lower than the load, thereby significantly reducing the total switching loss. In addition, a thermal balancing scheme is proposed to alleviate the thermal stress imbalance between the desynchronized GaN HEMTs. The operating principle and design guidelines of the desynchronizable paralleling scheme are detailed. Finally, experimental results from multi-pulse and continuous tests of GaN HEMTs are provided to verify the advantages of the proposed paralleling scheme in reducing light-load switching loss and improving light-load efficiency.

Quadrilateral Current Mode Paralleling of Power MOSFETs for Zero-Voltage Switching

“…In contrast with the direct parallel showing in Fig. 1(a), the current imbalance caused by the mismatches of transistors and parasitic parameters can be well mitigated by the added DM inductors [5], [37] showing in Fig. 1(b).…”

“…1(b). The DM inductors are typical of much lower inductance than the output filter inductance, and they can be either uncoupled [5] or inversely coupled [37] in implementation.…”

“…Structures of (a) conventional direct and (b) DM inductor-based parallel power MOSFETs. The DM inductors can be either uncoupled [5] or inversely coupled [37]. two turn-off delays of gate signals, the switch-node (midpoint) voltages of the two parallel HB legs are asynchronous, i.e., v b lags behind v a by times of δ Lof f and δ Hof f at their rising and falling edges, respectively.…”

“…Therefore, it is necessary or even unavoidable to connect multiple WBG power transistors in parallel in high-power applications [3]- [7]. Additionally, the parallel connection of multiple low-current WBG power transistors can be more cost-effective than employing a single high-current transistor [5]- [7].…”

“…By utilizing the phaseshedding technique [23], [24], the effective number of parallel transistor legs can be adjusted at different loads, which reduces the switching loss at partial loads. In order to lower the partialload switching loss, while simultaneously achieving thermal balance among parallel transistors, a desynchronized control scheme is proposed in [5]; however, only part of the parallel transistors can achieve the zero-voltage switching (ZVS).…”