Detailed and clock-driven simulation for HPC interconnection network

Zhou, Wen‐Hao; Chen, Juan; Wang, Qian; Dong, Dezun; Tang, Yuhua

doi:10.1007/s11704-016-5035-3

Cited by 3 publications

(1 citation statement)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…An arrival sequence is generated in each set. These sequences are used to simulate the order in which the OS allocates resources for actual jobs.NPB[10] traces with 4 and 8(9 for BT and SP) and 16 processes are get by HPC-NetSim [11]. An arrival sequence is generated for NPB.…”

Section: Experimental Platformmentioning

confidence: 99%

Network-on-Chip Aware Task Mappings

Sun

Dong

Chen

et al. 2020

Communications in Computer and Information Science

Self Cite

View full text Add to dashboard Cite

Energy and power density have forced the industry to introduce many-cores where a large number of processor cores are integrated into a single chip. In such settings, the communication latency of the network on chip (NoC) could be performance bottleneck of a multi-core and many-core processor. Unfortunately, existing approaches for mapping the running tasks to the underlying hardware resources often ignore the impact of the NoC, leading to sub-optimal performance and energy efficiency. This paper presents a novel approach to allocating NoC resource among running tasks. Our approach is based on the topology partitioning of the shared routers of the NoC. We evaluate our approach by comparing it against two state-of-the-art methods using simulation. Experimental results show that our approach reduces the NoC communication latency by 5.19% and 2.99%, and the energy consumption by 17.94% and 12.68% over two competitive approaches.

show abstract

Section: Experimental Platformmentioning

confidence: 99%