Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities

Tao, Jie; Karl, Wolfgang

doi:10.1145/1190095.1190174

Cited by 6 publications

(4 citation statements)

References 16 publications

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“…Detecting Capacity Misses: Tao et al propose a cache simulator that can identify cache capacity misses using the reuse distance for each memory access [51]. Nikos et al propose another cache simulation methodology [41].…”

Section: Related Workmentioning

confidence: 99%

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CachePerf: A Unified Cache Miss Classifier via Hybrid Hardware Sampling

Zhou,

Steven,

Yang

et al. 2022

Preprint

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The cache plays a key role in determining the performance of applications, no matter for sequential or concurrent programs on homogeneous and heterogeneous architecture. Fixing cache misses requires to understand the origin and the type of cache misses. However, this remains to be an unresolved issue even after decades of research. This paper proposes a unified profiling tool-CachePerf-that could correctly identify different types of cache misses, differentiate allocator-induced issues from those of applications, and exclude minor issues without much performance impact. The core idea behind CachePerf is a hybrid sampling scheme: it employs the PMU-based coarse-grained sampling to select very few susceptible instructions (with frequent cache misses) and then employs the breakpoint-based fine-grained sampling to collect the memory access pattern of these instructions. Based on our evaluation, CachePerf only imposes 14% performance overhead and 19% memory overhead (for applications with large footprints), while identifying the types of cache misses correctly. CachePerf detected 9 previous-unknown bugs. Fixing the reported bugs achieves from 3% to 3788% performance speedup. CachePerf will be an indispensable complementary to existing profilers due to its effectiveness and low overhead. CCS Concepts: • Software and its engineering → Multiprocessing / multiprogramming / multitasking; • Computer systems organization → Real-time operating systems.

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Section: Related Workmentioning

confidence: 99%

“…for development phases [49,52]. To solve such issues, many sampling-based tools, such as perf [10], oprofile [31], are proposed to reduce the profiling overhead.…”

mentioning

confidence: 99%

CachePerf: A Unified Cache Miss Classifier via Hybrid Hardware Sampling

Zhou,

Steven,

Yang

et al. 2022

Preprint

View full text Add to dashboard Cite

show abstract

“…Cache miss classification approaches can be divided into four major categories: trace-driven simulation, analytical modeling, custom hardware based approach, and PMU-based sampling technique. Trace-driven Cache Simulators [34], [27], [46] take memory access traces as input and simulate underlying cache to capture the behavior of the trace. This simulation of cache model can provide a theoretically accurate classification of cache misses by tracking memory references and reuse in the trace.…”

Section: Conflict Miss Detection and Optimizationmentioning

confidence: 99%

Lightweight detection of cache conflicts

Roy

Song

Krishnamoorthy

et al. 2018

Proceedings of the 2018 International Symposium on Code Generation and Optimization - CGO 2018

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In memory hierarchies, caches perform an important role in reducing average memory access latency. Minimizing cache misses can yield significant performance gains. As set-associative caches are widely used in modern architectures, capacity and conflict cache misses co-exist. These two types of cache misses require different optimization strategies. While cache misses are commonly studied using cache simulators, state-of-the-art simulators usually incur hundreds to thousands of times a program's execution runtime. Moreover, a simulator has difficulty in simulating complex real hardware. To overcome these limitations, measurement methods are proposed to directly monitor program execution on real hardware via performance monitoring units. However, existing measurement-based tools either focus on capacity cache misses or do not distinguish capacity and conflict cache misses. In this paper, we design and implement CCProf, a lightweight measurement-based profiler that identifies conflict cache misses and associates them with program source code and data structures. CCProf incurs moderate runtime overhead that is at least an order of magnitude lower than simulators. With the evaluation on a number of representative programs, CCProf is able to guide optimizations on cache conflict misses and obtain nontrivial speedups.

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“…A number of other cache simulators have been proposed [24], including CProf [17] and valgrind's cachegrind module [22,23]. Most of these simulators are similar to MemSpy, differing in the amount of programmer annotations or instrumentation necessary to run the tool.…”

Section: Data Profilersmentioning

confidence: 99%

Locating cache performance bottlenecks using data profiling

Pesterev

Zeldovich

Morris

2010

Proceedings of the 5th European Conference on Computer Systems

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Effective use of CPU data caches is critical to good performance, but poor cache use patterns are often hard to spot using existing execution profiling tools. Typical profilers attribute costs to specific code locations. The costs due to frequent cache misses on a given piece of data, however, may be spread over instructions throughout the application. The resulting individually small costs at a large number of instructions can easily appear insignificant in a code profiler's output.DProf helps programmers understand cache miss costs by attributing misses to data types instead of code. Associating cache misses with data helps programmers locate data structures that experience misses in many places in the application's code. DProf introduces a number of new views of cache miss data, including a data profile, which reports the data types with the most cache misses, and a data flow graph, which summarizes how objects of a given type are accessed throughout their lifetime, and which accesses incur expensive cross-CPU cache loads. We present two case studies of using DProf to find and fix cache performance bottlenecks in Linux. The improvements provide a 16-57% throughput improvement on a range of memcached and Apache workloads.

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Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities

Cited by 6 publications

References 16 publications

CachePerf: A Unified Cache Miss Classifier via Hybrid Hardware Sampling

CachePerf: A Unified Cache Miss Classifier via Hybrid Hardware Sampling

Lightweight detection of cache conflicts

Locating cache performance bottlenecks using data profiling

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