2018
DOI: 10.1007/s10836-018-5714-0
|View full text |Cite
|
Sign up to set email alerts
|

Detectability Challenges of Bridge Defects in FinFET Based Logic Cells

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1

Citation Types

0
3
0

Year Published

2018
2018
2023
2023

Publication Types

Select...
3
1
1

Relationship

1
4

Authors

Journals

citations
Cited by 5 publications
(3 citation statements)
references
References 35 publications
0
3
0
Order By: Relevance
“…The probability of occurrence of the short defects depends on the memory array architecture and how its layout is made. Typically, wider lines placed closer to other lines are more likely to present bridge defects [29]. The defects that are shown in Fig.…”
Section: Short Defects That Can Be Detectedmentioning
confidence: 99%
“…The probability of occurrence of the short defects depends on the memory array architecture and how its layout is made. Typically, wider lines placed closer to other lines are more likely to present bridge defects [29]. The defects that are shown in Fig.…”
Section: Short Defects That Can Be Detectedmentioning
confidence: 99%
“…Semiconductors with complex three‐dimensional (3D) structures are widely used in the current area of nanoscale manufacturing (Forero et al ., ). An in‐wafer 3D multiparametric measurement with nanoscale resolution is increasingly in demand to guarantee manufacturing accuracy and optimise process control (Yang et al ., ; Zhang et al ., ; IEEE Xplore Digital Library, ).…”
Section: Introductionmentioning
confidence: 99%
“…Resistive opens and resistive bridges result often in SDFs [1,2,3] which are hard to detect during production testing. Since they may evolve rather early in the circuits lifetime and turn into catastrophic faults, they have to be covered during the test of high-quality systems [4,5,6].…”
Section: Introductionmentioning
confidence: 99%