Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey

Doumar, Abderrahim; Ito, Hideo

doi:10.1109/tvlsi.2002.801609

Cited by 47 publications

(14 citation statements)

References 73 publications

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“…The most widely used test technique is a BIST that uses the programmability of the FPGA [1], [2], [5]. In this technique, LBs have three roles: as test targets, TPGs, and ORAs.…”

Section: Related Workmentioning

confidence: 99%

An Easily Testable Routing Architecture and Prototype Chip

Inoue

Koga

Amagasaki

et al. 2012

IEICE Trans. Inf. & Syst.

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SUMMARYGenerally, a programmable LSI such as an FPGA is difficult to test compared to an ASIC. There are two major reasons for this. The first is that an automatic test pattern generator (ATPG) cannot be used because of the programmability of the FPGA. The other reason is that the FPGA architecture is very complex. In this paper, we propose a new FPGA architecture that will simplify the testing of the device. The base of our architecture is general island-style FPGA architecture, but it consists of a few types of circuit blocks and orderly wire connections. This paper also presents efficient test configurations for our proposed architecture. We evaluated our architecture and test configurations using a prototype chip. As a result, the chip was fully tested using our configurations in a short test time. Moreover, our architecture can provide comparable performance to a conventional FPGA architecture. key words: design for testability, homogeneous architecture, test method, prototype chip

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“…The most widely used test technique is a BIST that uses the programmability of the FPGA [1], [2], [5]. In this technique, LBs have three roles: as test targets, TPGs, and ORAs.…”

Section: Related Workmentioning

confidence: 99%

An Easily Testable Routing Architecture and Prototype Chip

Inoue

Koga

Amagasaki

et al. 2012

IEICE Trans. Inf. & Syst.

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“…Most of the earlier works focused on tolerating the manufacturing defects and aging faults and manufacturing defects at either device level or configuration level using offline FT methods [2], [10]- [15]. However, provision of online FT is required to cater SEUs and software faults.…”

Section: Related Workmentioning

confidence: 99%

A Novel Approach for Providing Fault Tolerance to FPGA-Based Reconfigurable Systems

Sharma¹,

Chakraverty²

2012

IJET

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Abstract-Thedynamically reconfigurable Field Programmable Gate Arrays (FPGAs) are most frequently employed for developing adaptive embedded systems. They are also being increasingly used as co-processors in high performance computing applications. For these systems to be fielded in harsh environments such as those encountered in space, extra-terrestrial locations and regions of extreme conditions on the earth, one must adopt fault tolerant design techniques to ensure uninterrupted and reliable operation despite the occurrence of faults. Commercial Off-the-Shelf (COTS) FPGA components offer a cost effective design trajectory where the designer can choose among a rich variety of FT approaches and techniques. This paper compares the various FT techniques and proposes a novel method in which these techniques can work together to provide a synergetic approach for fault tolerant FPGA design.

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“…Double and Triple Modular Redundancy (DMR and TMR) are examples of design techniques that replicate parts of a design with the aim of yield enhancement as well as chip reliability improvement. Embedded FPGAs have also been used for yield improvement [5], [6]. However, these methods are costly because they incur significant area or performance overhead.…”

Section: Introductionmentioning

confidence: 99%

On error tolerance and Engineering Change with Partially Programmable Circuits

Mangassarian

Yoshida

Veneris

et al. 2012

17th Asia and South Pacific Design Automation Conference

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Abstract-The growing size, density and complexity of modern VLSI chips are contributing to an increase in hardware faults and design errors in the silicon, decreasing manufacturing yield and increasing the design cycle. The use of Partially Programmable Circuits (PPCs) has been recently proposed for yield enhancement with very small overhead. This new circuit structure is obtained from conventional logic by replacing some subcircuits with programmable LUTs. The present paper lays the theoretical groundwork for evaluating PPCs with Quantified Boolean Formula (QBF) satisfiability. First, QBF models are constructed to calculate the fault tolerance and design error tolerance of a PPC, namely the percentages of faults and design errors that can be masked using LUT reconfigurations. Next, zero-cost Engineering Change Order (ECO) in PPCs is investigated. QBF formulations are given for performing ECOs, and for quantifying the ECO coverage of a PPC architecture. Experimental results are presented evaluating PPCs from [1], demonstrating the applicability and accuracy of the proposed formulations.

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Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey

Cited by 47 publications

References 73 publications

An Easily Testable Routing Architecture and Prototype Chip

An Easily Testable Routing Architecture and Prototype Chip

A Novel Approach for Providing Fault Tolerance to FPGA-Based Reconfigurable Systems

On error tolerance and Engineering Change with Partially Programmable Circuits

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