Detection of Faults in SRAM Using Transient Current Testing

Abstract

Fast development of memory devices cause more area occupation of memory in a chip and the strong market competition have increased the standards of the produced memories. The increased demand on reliability has, in turn, stressed the importance of failure analysis and device testing techniques. More and more effort and thought is being dedicated to the study of testing memory devices with regards to new fault models, fault diagnosis and new memory architectures. In order to detect these faults, March test has been widely used. However, some defects on SRAM cells may not be detected by the conventional March tests. This detection of defects in CMOS SRAM has been a time consuming process. Hence we go for current testing method. This paper implements a transient current testing (I DDT ) method to detect defects in CMOS SRAM cells. By monitoring a transient current pulse during a transition write operation or a read operation, defects can be detected. In order to measure the transient current pulse, a current monitoring circuit is designed.