Detection of Hardware Trojans in Third-Party Intellectual Property Using Untrusted Modules

Reece, Trey; Robinson, William H.

doi:10.1109/tcad.2015.2459038

Cited by 11 publications

(3 citation statements)

References 33 publications

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“…The focus of our work differs from [32], as we investigate design-fortrust techniques to determine the configuration of the MPSoC system that meets the performance requirements and reduce energy. To reduce the runtime cost, Reece et al proposed a technique for identifying hardware trojans with logic-based payloads at design time [33]. However, it cannot be applied to large circuits due to the limited software capacity [13].…”

Section: A Trojans Detection In 3pipsmentioning

confidence: 99%

Designing Energy-Efficient MPSoC with Untrustworthy 3PIP Cores

Sun

Jiang

Lam

et al. 2020

IEEE Trans. Parallel Distrib. Syst.

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The adoption of large-scale MPSoCs and the globalization of the IC design flow give rise to two major concerns: high power density due to continuous technology scaling and security due to the untrustworthiness of the third-party intellectual property (3PIP) cores. However, little work has been undertaken to consider these two critical issues jointly during the design stage. In this paper, we propose a design methodology that minimizes the energy consumption while simultaneously protecting the MPSoC against the effects of hardware trojans. The proposed methodology consists of three main stages: 1) Task scheduling to introduce core diversity in the MPSoC in order to detect the presence of malicious modifications in the cores, or mute their effects at runtime, 2) Vendor assignment to the cores using a novel heuristic that chooses vendor-specific cores with operating speed that minimizes the total energy consumption of the MPSoC, and 3) Explore optimization opportunities for further energy savings by minimizing idle periods on the cores, which are caused by the inter-task data dependencies. Experimental results show that our solutions consume only 1/3 energy of existing solutions without increasing schedule length while satisfying the security constraints.

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Section: A Trojans Detection In 3pipsmentioning

confidence: 99%

Designing Energy-Efficient MPSoC with Untrustworthy 3PIP Cores

Sun

Jiang

Lam

et al. 2020

IEEE Trans. Parallel Distrib. Syst.

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“…Significant research efforts have been undertaken to detect such security threats. There are several proposed solutions related to digital systems [10]. However, for the cryptography systems utilizing analog chaotic circuits the security issues are still open [6].…”

Section: Hardware Trojansmentioning

confidence: 99%

“…As discussed in [6][7][8][9][10], the security issues and protection against HTs is a key problem in modern electronics and computer engineering. In this paper we discuss HTs that may easily be implemented and integrated with the PCB modules in chaotic analog generators.…”

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confidence: 99%

Hardware Trojans detection in chaos-based cryptography

Melosik

Śniatała

Marszałek

2017

Bulletin of the Polish Academy of Sciences Technical Sciences

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Abstract. The paper deals with the security problems in chaotic-based cryptography. In particular, the 0-1 test for chaos is used to detect hardware Trojans in electronic circuits -generators of chaotic bit sequences. The proposed method of detecting hardware Trojans is based on analyzing the original bit sequences through the 0-1 test yielding a simple result, either a number close to 1, when the examined bit sequence is chaotic, or a number close to 0, when the sequence is non-chaotic. A complementary result is a graph of translation variables q c and p c which form a basis of the 0-1 test. The method does not require any extra corrections and can be applied to relatively short sequences of bits. This makes the method quite attractive as the security problems are dealt with at the chaotic generator level, with no need to apply any extractors of randomness. The method is illustrated by numerical examples of simulated Trojans in chaotic bit generators based on the analog Lindberg circuit as well as a discrete system based on the logistic map.Key words: chaos-based cryptography, hardware Trojans, 0-1 test for chaos, bit generators. sequences is to use chaotic circuits. Such an approach is straightforward when compared to the use of quantum modules, which require significantly larger areas on PCBs. A random sequence generator can be integrated with a security module or it can itself be a separate module. The security issues of embedded systems, such as PCBs, were first discussed in [6]. However, [6] does not discuss the security problems and hardware Trojan attacks on random sequence generators based on chaotic circuits. This paper deals with such problems based on testing of chaotic signals by the 0-1 test for chaos. The result of such test is two-fold: a single number, close to either 0 or 1, and a visual two-dimensional plot of the so-called translation variables q c and p c , that in future might be implemented online in real time. Hardware Trojans detection in chaos-based cryptographyAs discussed in [6][7][8][9][10], the security issues and protection against HTs is a key problem in modern electronics and computer engineering. In this paper we discuss HTs that may easily be implemented and integrated with the PCB modules in chaotic analog generators. We also discuss HTs implemented through FPGA in chaotic discrete generators.

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