Determining Optimal Coherency Interface for Many-Accelerator SoCs Using Bayesian Optimization

Bhardwaj, Kshitij; Havasi, Marton; Yao, Yuan; Brooks, David; Lobato, Jose Miguel Hernendez; Wei, Gu-Yeon

doi:10.1109/lca.2019.2910521

Cited by 10 publications

(12 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Performing design space exploration manually leads to inefficient and time-consuming processes. Approaches based on hyperparameter optimization prove to be very effective in optimizing unknown objective functions as stated in works presented in [3,21]; they are more powerful than heuristic optimization in terms of convergence and quality of obtained solutions.…”

Section: Hyperparameter Optimization Methodsmentioning

confidence: 99%

See 1 more Smart Citation

Design Space Exploration of Heterogeneous-Accelerator SoCs with Hyperparameter Optimization

Cong

Charot

2021

Proceedings of the 26th Asia and South Pacific Design Automation Conference

View full text Add to dashboard Cite

Modern SoC systems consist of general-purpose processor cores augmented with large numbers of specialized accelerators. Building such systems requires a design flow allowing the design space to be explored at the system level with an appropriate strategy. In this paper, we describe a methodology allowing to explore the design space of power-performance heterogeneous SoCs by combining an architecture simulator (gem5-Aladdin) and a hyperparameter optimization method (Hyperopt). This methodology allows different types of parallelism with loop unrolling strategies and memory coherency interfaces to be swept. The flow has been applied to a convolutional neural network algorithm. We show that the most energy efficient architecture achieves a 2x to 4x improvement in energy-delay-product compared to an architecture without parallelism. Furthermore, the obtained solution is more efficient than commonly implemented architectures (Systolic, 2D-mapping, and Tiling). We also applied the methodology to find the optimal architecture including its coherency interface for a complex SoC made up of six accelerated-workloads. We show that a hybrid interface appears to be the most efficient; it reaches 22% and 12% improvement in energy-delay-product compared to just only using non-coherent and only LLC-coherent models, respectively.

show abstract

Section: Hyperparameter Optimization Methodsmentioning

confidence: 99%

“…These techniques offer interesting opportunities for architecture simulation, especially in the early stages of the design process. Bhardwaj et al present in [3] a Bayesian optimizationbased framework for determining the optimal hybrid coherency interface for many-accelerator SoCs in terms of performance.…”

Section: Related Workmentioning

confidence: 99%

Design Space Exploration of Heterogeneous-Accelerator SoCs with Hyperparameter Optimization

Cong

Charot

2021

Proceedings of the 26th Asia and South Pacific Design Automation Conference

View full text Add to dashboard Cite

show abstract

“…Experimental results show that CGRA performance can be improved by an average of 2.53× while saving dozens of processing elements. The Bayesian Cache Coherence Optimization framework [33] can determine which type of cache coherence interface to use for various accelerators in a system. This results in a performance-aware hybrid coherency interface suited for different applications.…”

Section: Taxonomy Of Existing Projectsmentioning

confidence: 99%

A Survey on Domain-Specific Memory Architectures

Soldavini

Pilato

2021

JICS

View full text Add to dashboard Cite

The never-ending demand for high performance and energy efficiency is pushing designers towards an increasing level of heterogeneity and specialization in modern computing systems. In such systems, creating efficient memory architectures is one of the major opportunities for optimizing modern workloads (e.g., computer vision, machine learning, graph analytics, etc.) that are extremely data-driven. However, designers demand proper design methods to tackle the increasing design complexity and address several new challenges, like the security and privacy of the data to be elaborated.This paper overviews the current trend for the design of domain-specific memory architectures. Domain-specific architectures are tailored for the given application domain, with the introduction of hardware accelerators and custom memory modules while maintaining a certain level of flexibility. We describe the major components, the common challenges, and the state-of-the-art design methodologies for building domain-specific memory architectures. We also discuss the most relevant research projects, providing a classification based on our main topics.

show abstract

“…Our EXMA is connected to a CPU processor as a looselycoupled non-coherent accelerator [50], [51] by a Network-on-Chip (NoC). EXMA accesses DRAM via two DMA-dedicated planes of the NoC, bypassing the cache hierarchy of the CPU.…”

Section: ) System Integrationmentioning

confidence: 99%

“…The EXMA data region must be flushed from the CPU cache hierarchy before FM-Index searches start. We chose the noncoherent model [50] for better performance, since the memory footprint of FM-Index searches is always larger than the CPU LLC capacity.…”

Section: ) System Integrationmentioning

confidence: 99%

EXMA: A Genomics Accelerator for Exact-Matching

Jiang

Zokaee

2021

Preprint

View full text Add to dashboard Cite

Genomics is the foundation of precision medicine, global food security and virus surveillance. Exact-match is one of the most essential operations widely used in almost every step of genomics such as alignment, assembly, annotation, and compression. Modern genomics adopts Ferragina-Manzini Index (FM-Index) augmenting space-efficient Burrows-Wheeler transform (BWT) with additional data structures to permit ultra-fast exactmatch operations. However, FM-Index is notorious for its poor spatial locality and random memory access pattern. Prior works create GPU-, FPGA-, ASIC-and even process-in-memory (PIM)based accelerators to boost FM-Index search throughput. Though they achieve the state-of-the-art FM-Index search throughput, the same as all prior conventional accelerators, FM-Index PIMs process only one DNA symbol after each DRAM row activation, thereby suffering from poor memory bandwidth utilization.In this paper, we propose a hardware accelerator, EXMA, to enhance FM-Index search throughput. We first create a novel EXMA table with a multi-task-learning (MTL)-based index to process multiple DNA symbols with each DRAM row activation. We then build an accelerator to search over an EXMA table. We propose 2-stage scheduling to increase the cache hit rate of our accelerator. We introduce dynamic page policy to improve the row buffer hit rate of DRAM main memory. We also present CHAIN compression to reduce the data structure size of EXMA tables. Compared to state-of-the-art FM-Index PIMs, EXMA improves search throughput by 4.9×, and enhances search throughput per Watt by 4.8×.

show abstract

Determining Optimal Coherency Interface for Many-Accelerator SoCs Using Bayesian Optimization

Cited by 10 publications

References 9 publications

Design Space Exploration of Heterogeneous-Accelerator SoCs with Hyperparameter Optimization

Design Space Exploration of Heterogeneous-Accelerator SoCs with Hyperparameter Optimization

A Survey on Domain-Specific Memory Architectures

EXMA: A Genomics Accelerator for Exact-Matching

Contact Info

Product

Resources

About