Determining the thermal expansion coefficient of thin films for a CMOS MEMS process using test cantilevers

Abstract

Many standard CMOS processes, provided by existing foundries, are available. These standard CMOS processes, with stacking of various metal and dielectric layers, have been extensively applied in integrated circuits as well as micro-electromechanical systems (MEMS). It is of importance to determine the material properties of the metal and dielectric films to predict the performance and reliability of micro devices. This study employs an existing approach to determine the coefficients of thermal expansion (CTEs) of metal and dielectric films for standard CMOS processes. Test cantilevers with different stacking of metal and dielectric layers for standard CMOS processes have been designed and implemented. The CTEs of standard CMOS films can be determined from measurements of the out-of-plane thermal deformations of the test cantilevers. To demonstrate the feasibility of the present approach, thin films prepared by the Taiwan Semiconductor Manufacture Company 0.35 μm 2P4M CMOS process are characterized. Eight test cantilevers with different stacking of CMOS layers and an auxiliary Si cantilever on a SOI wafer are fabricated. The equivalent elastic moduli and CTEs of the CMOS thin films including the metal and dielectric layers are determined, respectively, from the resonant frequency and static thermal deformation of the test cantilevers. Moreover, thermal deformations of cantilevers with stacked layers different to those of the test beams have been employed to verify the measured CTEs and elastic moduli.

Curvature of BEOL Cantilevers in CMOS-MEMS Processes

“…The variability of process and design parameters is particularly important in the case of commercial devices, which need to achieve the required levels of performance in the full range of process variability. The curvature of the BEOL layers plays a very important role in this sense and, although there are plenty of works dealing with curvature and residual stresses [5,[9][10][11][12][13][14], no large studies regarding the curvature of the BEOL metal layers of CMOS-MEMS processes are available in the literature.…”

A CMOS-MEMS BEOL 2-axis Lorentz-Force Magnetometer with Device-Level Offset Cancellation

“…One of the key concerns when designing MEMS sensors using the BEOL metal layers is the curvature of the device structures due to BEOL thin metals residual stress and different temperature coefficients of stacked layers [ 19 , 25 , 26 , 27 , 30 , 31 ]. The device proposed in this article is not an exception as described in Section 5.2 , even though the final device curvature was minimized by using various metal and oxide layers stacked together using long vias, a technique used in numerous CMOS-MEMS devices in the literature [ 25 , 26 , 27 ].…”

Nanoscale Investigation of Local Thermal Expansion at SrTiO3 Grain Boundaries by Electron Energy Loss Spectroscopy

“…Figure compares the temperature-induced plasmon peak shift in Σ5 and 45° GBs. Since the thickness dependence of CTE has been reported in several early works, ,, the thickness of two GBs was carefully checked during the EELS acquisition. The thickness was estimated as 59–86 nm and 69–88 nm for two GBs, respectively, by the Fourier log-ratio method using EELS intensity and inelastic mean free path of SrO (126 nm).…”