Deterministic Assembly of In_0.53Ga_0.47As p⁺-i-n⁺ Nanowire Junctions for Tunnel Transistors

Abstract

Electric-field-assisted deterministic assembly is used to position arrays of p + -i-n + In 0.53 Ga 0.47 As nanowires on a Si substrate for device integration. Forces induced on the solution-suspended wires by a spatially varying, nonuniform electric field determines the position of each wire with respect to lithographic features on the substrate. The electrical properties of the sub-50 nm diameter In 0.53 Ga 0.47 As junctions with a 100 nm thick unintentionally doped channel were characterized after adding source and drain contacts. The junctions showed clear rectification, with a forward bias ideality factors as low as 1.8, and reverse leakage current as small as 20 pA at a −1 V bias. This represents an important step towards demonstrating an In 0.53 Ga 0.47 As-based nanowire tunnel transistor. IntroductionAs metal oxide semiconductor field-effect transistor (MOSFET) power densities continue to rise at each technology node, tunnel field-effect transistors (TFETs) have emerged as an attractive low-power MOSFET replacement candidate. [1][2][3][4][5][6][7] In contrast to MOSFETs, TFETs have been shown to be able to break the 60 mV/dec subthreshold slope (SS) limit 3-4 because the gate controls tunneling through a barrier rather than emission over it, which filters out the high and low energy tails of the Fermi-Dirac distribution. Because nanowire devices have a circular geometry and a confined-volume body, a gate that wraps around the nanowire will provide excellent electrostatic control over the channel. [8][9][10] The improved channel control is expected to both reduce the S and improve the onstate current of nanowire TFETs. 7-8 Moreover, confinement effects such as the volume inversion of carriers 11 or the reduction of transverse momentum conservation requirements 12 may further enhance tunneling probabilities in nanowire systems.Nanowires grown by the vapor-liquid-solid (VLS) method have the capability to reach diameters below 10 nm, 13 and also permit doped junctions and heterojunctions to be formed in situ, allowing for the synthesis of complex device structures. However, it has been difficult to achieve the extremely abrupt profile in the heavily doped source and ECS Transactions, 45 (4) 129-136 (2012) 10.1149/1.3700461 © The Electrochemical Society 129 drain junction required for high performance devices using VLS growth. This paper describes the integration and characterization of In 0.53 Ga 0.47 As p + -i-n + nanowire junctions that are fabricated by high-aspect-ratio reactive ion etching (RIE) of device layers grown by molecular beam epitaxy (MBE). The dense arrays of sub-50 nm diameter vertically oriented nanowires are released from the InP growth substrate by selective etching, and are assembled into lateral device arrays on a Si substrate by electric-field assisted assembly. The source and drain metal contacts are deposited on the p + and n + segments of the wires, and the current-voltage (I-V) properties are measured under different ambient conditions. The etched junctions exhibit clear rectifying p...