Deterministic circuit variation for anti-tamper applications

McDonald, J. Todd; Kim, Yong; Koranek, Daniel

doi:10.1145/2179298.2179376

Cited by 10 publications

(7 citation statements)

References 6 publications

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“…Component Obfuscation: Many reverse engineering techniques engage in component recognition. Techniques have been proposed to increase the complexity of delineating components by changing the logic gates at the output and input boundaries of connected blocks (Boundary Blurring) [17], replacing an entire circuit with an obfuscated equivalent (Component Fusion) [18], [19] and targeting interconnections between two blocks for encryption [20].…”

Section: B Capabilities Of the Attackermentioning

confidence: 99%

Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques

Vijayakumar

Patil

Holcomb

et al. 2017

IEEE Trans.Inform.Forensic Secur.

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The threat of hardware reverse engineering is a growing concern for a large number of applications. A main defense strategy against reverse engineering is hardware obfuscation. In this work we investigate physical obfuscation techniques, which perform alterations of circuit elements that are difficult or impossible for an adversary to observe. Examples of such stealthy manipulations are changes in the doping concentrations or dielectric manipulations. An attacker will, thus, extract a netlist which does not correspond to the logic function of the device-under-attack. This approach of camouflaging has garnered recent attention in the literature.In this paper, we expound on this promising direction to conduct a systematic end-to-end study of the VLSI design process to find multiple ways to obfuscate a circuit for hardware security. This paper makes three major contributions. First, we provide a categorization of the available physical obfuscation techniques as it pertains to various design stages. There is a large and multidimensional design space for introducing obfuscated elements and mechanisms, and the proposed taxonomy is helpful for a systematic treatment. Second, we provide a review of the methods that have been proposed or in use. Third, we present recent and new device and logic-level techniques for design obfuscation. For each technique considered, we discuss feasibility of the approach and assess likelihood of its detection. Then we turn our focus to open research questions, and conclude with suggestions for future research directions.

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Section: B Capabilities Of the Attackermentioning

confidence: 99%

Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques

Vijayakumar

Patil

Holcomb

et al. 2017

IEEE Trans.Inform.Forensic Secur.

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“…By changing the hardware, generated circuits can cause an attacker's efforts to increase substantially without causing major increases in performance costs [18].…”

Section: Intellectual Property Protection and Anti-tampermentioning

confidence: 99%

“…Since any program can be represented logically as a circuit, we can generate equivalent circuits to produce dynamic polymorphic variants. We have produced extensive work on program and circuit obfuscation related to this approach [16,18,19]. As Figure 4 depicts, we let P be a program, defined as a circuit, from which want to generate a set of equivalent circuits.…”

Section: Circuit Variantsmentioning

confidence: 99%

“…Numerous security applications have been transitioned into FPGA implementations to allow security applications to operate at real-time speeds, such as firewall and packet scanning uses on high speed networks without performance degradations [6,11,14,15]. FPGA security research exists into side-channel vulnerabilities and countermeasures [1,2,4], intellectual property protections [17,18,20,25], and anti-tamper applications [5,7].…”

Section: Introductionmentioning

confidence: 99%

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Software Security and Randomization through Program Partitioning and Circuit Variation

Andel

Whitehurst

McDonald

2014

Proceedings of the First ACM Workshop on Moving Target Defense

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The commodity status of Field Programmable Gate Arrays (FPGAs) has allowed computationally intensive algorithms, such as cryptographic protocols, to take advantage of faster hardware speed while simultaneously leveraging the reconfigurability and lower cost of software. Numerous security applications have been transitioned into FPGA implementations allowing security applications to operate at real-time speeds, such as firewall and packet scanning on high speed networks. However, the utilization of FPGAs to directly secure software vulnerabilities is seemingly non-existent.Protecting program integrity and confidentiality is crucial as malicious attacks through injected code are becoming increasingly prevalent. This paper lays the foundation of continuing research in how to protect software by partitioning critical sections using reconfigurable hardware. This approach is similar to a traditional coprocessor approach to scheduling opcodes for execution on specialized hardware as opposed to running on the native processor. However, the partitioned program model enables the programmer the ability to split portions of an application to reconfigurable hardware at compile time. The fundamental underlying hypothesis is that synthesizing portions of programs onto hardware can mitigate potential software vulnerabilities. Further, this approach provides an avenue for randomization or diversity for software layout and circuit variation.

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“…Component fusion [13] ensures replacement of the entire circuit during every iteration of the algorithm. It accomplishes this by partitioning the circuit into subcircuits and then targets hiding of known information based on original component definitions.…”

Section: Deterministic Component Fusionmentioning

confidence: 99%

Evaluating component hiding techniques in circuit topologies

McDonald

Kim

Koranek

et al. 2012

2012 IEEE International Conference on Communications (ICC)

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Security for Cyber physical systems includes not only guaranteeing operational security of data they process, but preventing malicious alteration of their execution due to knowledge of their underlying structure. With the advent of software in the form of reprogrammable hardware descriptions, protection of field programmable units from malicious reverse engineering and subversion becomes more critical. We compare four different white-box transformation algorithms aimed at hindering adversarial reverse engineering by changing component and signal configurations within combinational logic programs. We present security and efficiency analysis for these techniques and show positive results for achieving measurable hiding of signal and component information.

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Deterministic circuit variation for anti-tamper applications

Cited by 10 publications

References 6 publications

Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques

Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques

Software Security and Randomization through Program Partitioning and Circuit Variation

Evaluating component hiding techniques in circuit topologies

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