Deuce

Abstract

Phase Change Memory (PCM) is an emerging Non Volatile Memory (NVM) technology that has the potential to provide scalable high-density memory systems. While the non-volatility of PCM is a desirable property in order to save leakage power, it also has the undesirable effect of making PCM main memories susceptible to newer modes of security vulnerabilities, for example, accessibility to sensitive data if a PCM DIMM gets stolen. PCM memories can be made secure by encrypting the data. Unfortunately, such encryption comes with a significant overhead in terms of bits written to PCM memory, causing half of the bits in the line to change on every write, even if the actual number of bits being written to memory is small. Our studies show that a typical writeback modifies, on average, only 12% of the bits in the cacheline. Thus, encryption causes almost a 4x increase in the number of bits written to PCM memories. Such extraneous bit writes cause significant increase in write power, reduction in write endurance, and reduction in write bandwidth. To provide the benefit of secure memory in a write efficient manner this paper proposes Dual Counter Encryption (DEUCE). DEUCE is based on the observation that a typical writeback only changes a few words, so DEUCE reencrypts only the words that have changed. We show that DEUCE reduces the number of modified bits per writeback for a secure memory from 50% to 24%, which improves performance by 27% and increases lifetime by 2x.

Maternal periodontal disease and risk of preeclampsia: A meta-analysis

“…In our threat model, attackers can reveal the data by snooping the memory bus and physically stealing the non-volatile DIMM. The data integrity attacks [48] are beyond the scope of our paper like existing works [12], [38], [49], [58], [61], [62], which can be defended via Merkle tree based designs [18], [23], [45], [50].…”

“…To ensure data confidentiality, counter mode encryption (CME) has been widely used in existing NVM-based secure systems [12], [49], [58], [62]. The CME is executed in the memory controller and becomes transparent to applications.…”

“…The memory controller thus becomes the persistent domain in the ADR-based NVM system. To protect the data transiting in the memory bus, which exists in the threatened domain in the context of our threat model ( §II-A), the ADRbased NVM system leverages the CME [12], [49], [58], [62] in the memory controller to encrypt the data. As shown in Fig.…”

“…Unlike the disk and PM in the off-chip domain, the encryption/decryption latencies for the data in the on-chip memory controller significantly impact the system performance. To efficiently encrypt the data in the on-chip memory controller for data confidentiality, a low-overhead counter mode encryption (CME) scheme in the memory controller has been proposed and widely used in existing works [12], [49], [58], [62].…”

“…While prior designs mainly offer data confidentiality in the disks, NVM, and ADR-based NVM systems [12], [15], [20], [33], [38], [49], [58], [61], [62], few schemes discuss how to encrypt data in the eADR-based NVM systems when the CPU caches become persistent domain. Although the onchip caches are security domains [12], [14], [38], [45], [56], [57], [60], efficient encryption is still important for the cached data in the eADR-based NVM system for data confidentiality.…”