Proceedings of the 54th Annual Design Automation Conference 2017 2017
DOI: 10.1145/3061639.3062230
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Developing Dynamic Profiling and Debugging Support in OpenCL for FPGAs

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Cited by 12 publications
(9 citation statements)
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“…Additionally, this virtual architecture cannot be associated with or even applied to commercially available OpenCL-for-FPGA design tools. A framework for debugging and monitoring OpenCL-based FPGA designs was proposed in [43]. This framework is limited to capturing events and their sequences based on timestamps.…”
Section: Related Work On In-system Fpga Instrumentationmentioning
confidence: 99%
“…Additionally, this virtual architecture cannot be associated with or even applied to commercially available OpenCL-for-FPGA design tools. A framework for debugging and monitoring OpenCL-based FPGA designs was proposed in [43]. This framework is limited to capturing events and their sequences based on timestamps.…”
Section: Related Work On In-system Fpga Instrumentationmentioning
confidence: 99%
“…As for methodologies for debugging hardware generated from multi-threaded programs, one of the few contributions (besides the work of Goeders et al mentioned above [19]) is a work of Verma et al [47] targeting OpenCL for FPGAs. The authors describe open-source debug components, modeled both in the OpenCL language and in Verilog Hardware Description Language (HDL), that can be used for manual inspection of OpenCL kernels running on FPGA.…”
Section: Related Workmentioning
confidence: 99%
“…Debug support for circuits generated with HLS has received attention, but for designs synthesized from multi-threaded parallel programs the contributions are scarce. Current approaches focus on the low-level details of the infrastructure necessary for on-chip debugging [19,47]. Users need to explicitly instruct the tools about where to place tracepoints and manually inspect the traces to spot malfunctions.…”
Section: Introductionmentioning
confidence: 99%
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“…Work in [5,14,20,25] describe frameworks that allow users to specify debugging points in high-level language and synthesize hardware probes into the FPGA for analysis. They can be categorized into work that has more focus on verifying functional correctness [14,20] and work that has more focus on extracting performancerelated parameters [5,25]. Work in [14] describes how to record and replay the execution of optimized HLS-generated circuits.…”
Section: Related Workmentioning
confidence: 99%