2017
DOI: 10.1007/s00542-016-3267-7
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Development and reliability study of 3D WLCSP for CMOS image sensor using vertical TSVs with 3:1 aspect ratio

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Cited by 14 publications
(2 citation statements)
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“…To meet the urgent market demand of small package size and high reliability performance for automotive CIS application, wafer level chip scale packaging (WLCSP) technology, using through silicon vias (TSV), needs to be developed to replace current chip on board (COB) packages [ 19 , 20 , 21 , 22 ]. Three-dimensional WLCSP with TSV technology takes advantages in shorter electrical interconnection, small form factor, high yield, and low cost [ 23 , 24 , 25 , 26 , 27 , 28 ].…”
Section: Introductionmentioning
confidence: 99%
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“…To meet the urgent market demand of small package size and high reliability performance for automotive CIS application, wafer level chip scale packaging (WLCSP) technology, using through silicon vias (TSV), needs to be developed to replace current chip on board (COB) packages [ 19 , 20 , 21 , 22 ]. Three-dimensional WLCSP with TSV technology takes advantages in shorter electrical interconnection, small form factor, high yield, and low cost [ 23 , 24 , 25 , 26 , 27 , 28 ].…”
Section: Introductionmentioning
confidence: 99%
“…Previous works have focused on package fabrication, rather than reliability performance. The structure they introduced suffered different failure modes in reliability tests, such as pad delamination [ 21 ] and oxide crack [ 22 ], which were unacceptable in automotive application.…”
Section: Introductionmentioning
confidence: 99%