2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus) 2019
DOI: 10.1109/eiconrus.2019.8657285
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Development and Verification of Various Formats of Functional Blocks Libraries as a Part of the Design Flow for FPGAs

Tatiana V. Garbulina
1
,
V.M. Khvatov
2
,
D.A. Zheleznikov
3
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