Development Flow for On-Line Core Self-Test of Automotive Microcontrollers

Bernardi, P.; Luca, Sergio De; Sánchez, Ernesto; Sansonetti, A.

doi:10.1109/tc.2015.2498546

Cited by 62 publications

(18 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Computing these figures for a given STL also requires a new generation of tools called Functional Fault Simulators. Several recent works introduced guidelines on how to correctly generate STLs for CPUs [27], [28] and peripherals [29], how to speed up the FI experiments [30], how to maximize their fault coverage in the different scenarios (possibly minimizing the test time [31]), and how to re-use existing STLs.…”

Section: B Software Test Librariesmentioning

confidence: 99%

Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks

Silva

Bagbaba

Ruospo

et al. 2020

2020 IEEE 38th VLSI Test Symposium (VTS)

Self Cite

View full text Add to dashboard Cite

The current demands for autonomous driving generated momentum for an increase in research in the different technologies required for these applications. Nonetheless, the limited access to representative designs and industrial methodologies poses a challenge to the research community. Considering this scenario, there is a high demand for an open-source solution that could support development of research targeting automotive applications. This paper presents the current status of AutoSoC, an automotive SoC benchmark suite that includes hardware and software elements and is entirely open-source. The objective is to provide researchers with an industrial-grade automotive SoC that includes all essential components, is fully customizable, and enables analysis of functional safety solutions and automotive SoC configurations. This paper describes the available configurations of the benchmark including an initial assessment for ASIL B to D configurations.

show abstract

Section: B Software Test Librariesmentioning

confidence: 99%

Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks

Silva

Bagbaba

Ruospo

et al. 2020

2020 IEEE 38th VLSI Test Symposium (VTS)

Self Cite

View full text Add to dashboard Cite

show abstract

“…In [15], the authors introduced some solutions facing the issues raised by the usage of SBST solutions. In [16], the authors described multiple solutions adopted in real industry test cases. Similarly, some algorithms for automatically compacting existing test programs to reduce their size [17]- [19], or duration [20] have been recently proposed.…”

Section: Related Work In the Areamentioning

confidence: 99%

An On-Line Testing Technique for the Scheduler Memory of a GPGPU

2020

View full text Add to dashboard Cite

The highly parallel processing capabilities and reduced power performance of General Purpose Graphics Processing Units (GPGPUs) have been crucial factors for their massive use in multiple fields, such as multimedia and high-performance computing applications. Nowadays, more demanding areas, such as automotive, employ GPGPU devices where safety and reliability are mandatory design constraints. Nevertheless, the structural complexity, the transistor density, and the implementation in the latest silicon technologies introduce challenges to match safety and reliability requirements. In these technologies, wear-out and aging are factors that may significantly increase the occurrence of permanent faults during the lifetime operation. Moreover, these faults may generate unacceptable misbehaviors during the execution of an application. These constraints require devising new methods for in-field fault detection, thus verifying the integrity and correct behavior of the device during its whole operational life. This work proposes a technique to generate functional self-test programs targeting the detection of permanent static faults in the memory of the warp scheduler of a GPGPU. The proposed technique can translate fault primitives, which represent the effect of faults in a memory cell, into self-test functions and programs composed of a sequence of operations to excite the fault in the memory and to propagate its effects to a visible location, thus detecting its presence. We focused on the memory in the warp scheduler because it represents a crucial module for the device operation. Furthermore, this memory is present in each Streaming Multiprocessor (SM) of a GPGPU. Some experimental results to validate the method have been gathered, resorting to the NVIDIA Visual Profiler and the Nsight Debugger using the NVIDIA-GEFORCE GTX GPU platform and a structural fault simulator. The CUDA programming environment was used to implement the test procedures. INDEX TERMS Functional test, general purpose graphics processing units (GPGPUs), memory test, software-based self-test (SBST).

show abstract

“…Normally, Self-test procedures are developed according to a divide and conquer strategy. If the target module is a CPU, this is partitioned into submodules, and for each submodule, a specific Self-test procedure is developed [9]. The methodologies described in the previous sub-section represent a good solution for performing the fault grading of a single test procedure.…”

Section: B Fault Grading Of a Software Test Librarymentioning

confidence: 99%

Fault Grading Techniques of Software Test Libraries for Safety-Critical Applications

2019

Self Cite

View full text Add to dashboard Cite

The adoption of complex and technologically advanced integrated circuits (ICs) in safetycritical applications (e.g., in automotive) forced the introduction of new solutions to guarantee the achievement of the required reliability targets. One of these solutions lies in performing in-field test (i.e., the test performed when the device is already deployed in the mission environment) to detect faults that may arise in this phase of electronic circuit life. In this scenario, one increasingly adopted approach is based on the software test libraries (STLs), i.e., suitable code which is run by the CPU included in the system and is able to detect the existence of possible permanent faults both in the CPU itself and in the rest of the system. In order to assess the effectiveness of the STLs, fault simulation is performed, so that the achieved fault coverage (e.g., in terms of stuck-at faults) can be computed. This paper explains why the fault simulation of the STLs represents a different problem with respect to the classical fault simulation of test stimuli (for which very effective algorithms and tools are available), shows why it can be highly computationally expensive, and overviews some solutions to reduce the computational cost and possibly trade-off between results accuracy and cost.

show abstract

Development Flow for On-Line Core Self-Test of Automotive Microcontrollers

Cited by 62 publications

References 25 publications

Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks

Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks

An On-Line Testing Technique for the Scheduler Memory of a GPGPU

Fault Grading Techniques of Software Test Libraries for Safety-Critical Applications

Contact Info

Product

Resources

About