Development of 3-D silicon die stacked package using flip chip technology with micro bump interconnects

Vempati, Srinivasa Rao; Su, Nandar; Khong, Chee Houe; Lim, Ying Ying; Kripesh, V.; Lau, John H.; Liew, B.P.; Au, K. Y.; Tanary, S.; Fenner, Andy; Erich, Robert; Milla, Juan

doi:10.1109/ectc.2009.5074132

Cited by 37 publications

(9 citation statements)

References 5 publications

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“…With the achieved results and innovations, future demands in regard to next generation Flip Chip products for the medical [20], optoelectronics [21][ [22], microwave [23], and mobile [24] applications can be met.…”

Section: Discussionmentioning

confidence: 99%

Wafer Level Solder Bumping and Flip Chip Assembly with Solder Balls Down to 30μm

Oppert¹,

Dohle

Franke³

et al. 2011

International Symposium on Microelectronics

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The most important technology driver in the electronics industry is miniaturization mainly driven by size reduction on wafer level and cost. One of the interconnection technologies for fine pitch applications with the potential for highest integration and cost savings is Flip Chip technology. The commonly used method of generating fine pitch solder bumps is by electroplating the solder. This process is difficult to control or even impossible if it comes to ternary or quaternary alloys. The work described in this study addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping and the use of a very large variety of solder alloys. This flexibility in the selection of the solder materials and UBM stacks is a large advantage if it is essential to improve temperature cycling resistance, drop test resistance, or to increase electromigration lifetime. The technology allows rapid changeover between different low melting solder alloys. Tighter bump pitches and a better bump quality (no flux entrapment) are achievable than with screen printing of solder paste. Because no solder material is wasted, the material costs for precious metal alloys like Au80Sn20 are much lower than with other bumping processes. Solder bumps with a diameter between to date 30 μm and 500 μm as well as small and large batches can be manufactured with one cost efficient process. To explore this potential, cost-efficient solder bumping and automated assembly technologies for the processing of Flip Chips have been developed and qualified. Flip Chips used in this study are 10 mm by 10 mm in size, have a pitch of 100 μm and a solder ball diameter of 30 μm, 40 μm or 50μm, respectively. Wafer level solder application has been done using wafer level solder sphere transfer process or solder sphere jetting technology, respectively. The latter tool has been used for many years in the wafer level packaging industry for both Flip Chip and chip scale packaging applications. It is commonly known in the industry as a solder ball bumping equipment. For the described work the process was scaled down for processing solder spheres with a diameter of 30 μm what was never done before that way worldwide. The research has shown that the underfill process is one of the most crucial factors when it comes to Flip Chip miniaturization for high reliability applications. Therefore, high performance underfill material was qualified initially [1]. Final long term reliability testing has been done according to MIL-STD883G, method 1010.8, condition B up to thirteen thousand cycles with excellent performance of the highly miniaturized solder joints. SEM/EDX and other analysis techniques will be presented. Additionally, an analysis of the failure mechanism will be given and recommendations for key applications and further miniaturization will be outlined.

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Section: Discussionmentioning

confidence: 99%

Wafer Level Solder Bumping and Flip Chip Assembly with Solder Balls Down to 30μm

Oppert¹,

Dohle

Franke³

et al. 2011

International Symposium on Microelectronics

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“…Because of a multi-layer package is required, both wafer level package (WLP) [3] and chip stacked packages (CSP) [4] [5] have been researched. However, poor alignment and high cost limit the application of CSP"s. WLP, which provides extremely space efficient, low cost packaging, contamination-free 3D packaging and higher-quality products, is researched for future package trend.…”

Section: Figure2 Schematic Of a Chip-scale Atomic Clock Physics Packmentioning

confidence: 99%

Low temperature multi-layer wafer level package for chip scale atomic clock (CSAC)

Zhang

Zhu

et al. 2015

10th IEEE International Conference on Nano/Micro Engineered and Molecular Systems

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This paper demonstrates a five layers wafer level packaging. This technology has been specially developed for chip scale atomic clock system package. It includes a sealed vapor cell and two supports for vertical-cavity surface-emitting lasers and photodetector. The sealed cavity is achieved by Glass-Silicon-Glass (G-S-G) anodic bonding with high hermeticity, high reliability and low bonding temperature (400º C). The triple structure is supported by two silicon wafers. It is realized by photosensitive BCB adhesive bonding with good uniformity, relatively high mechanical strength (8Mpa) and low bonding temperature (250ºC ). The results show that over 60% of wafer is bonded with no void on the joint area and well aligned. At last, the stacked wafer is diced into individual chips.

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“…As with many other new technologies, TSVs still face many critical issues. In the development of TSVs, the following must be noted and understood (Lau, 2009a(Lau, , b, c, 2010a(Lau, , b, 2011Lau et al, 2010a, b;Lau and Tang, 2009;Yu et al, 2008aYu et al, , b, 2009aTang et al, 2010;Chen et al, 2008c;Premachandran et al, 2008;Zhang et al, 2009a, b;Hoe et al, 2009;Choi et al, 2009;Vempati et al, 2009;Khan et al, 2008Khan et al, , 2009Sekhar et al, 2008;Ho et al, 2008;Selvanayagam et al, 2009;Sekiguchi et al, 2006;Takahashi and Sekiguchi, 2006;Garrou et al, 2009;Ramm et al, 2008;Andry et al, 2008;Knickerbocker et al, 2008;Kumagai et al, 2008;Sunohara et al, 2008;Lee et al, 2007;Matsuo et al, 2000;Wong et al, 2006;Beica et al, 2008;Wolf et al, 2008;Henry et al, 2008):…”

Section: Critical Issues Of Tsvmentioning

confidence: 99%

Overview and outlook of through‐silicon via (TSV) and 3D integrations

Lau

2011

Microelectronics International

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286

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Purpose -The purpose of this paper is to focus on through-silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented. Design/methodology/approach -This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for highpower, high-performance, high pin-count, ultra fine-pitch, small real-estate, and low-cost applications. To achieve this, the design uses chip-to-chip interconnections through a passive TSV interposer in a 3D IC integration system-in-package (SiP) format with excellent thermal management. Findings -A generic, low-cost and thermal-enhanced 3D IC integration SiP with a passive interposer has been proposed for high-performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3D IC integration have been presented and discussed. Some important results and recommendations are summarized: the TSV/redistribution layer (RDL)/integrated passive devices passive interposer, which supports the high-power chips on top and low-power chips at its bottom, is the gut and workhorse of the current 3D IC integration design; with the passive interposer, it is not necessary to "dig" holes on the active chips. In fact, try to avoid making TSVs in the active chips; the passive interposer provides flexible coupling for whatever chips are available and/or necessary, and enhances the functionality and possibly the routings (shorter); with the passive interposer, the TSV manufacturing cost is lower because the requirement of TSV manufacturing yield is too high (.99.99 percent) for the active chips to bear additional costs due to TSV manufacturing yield loss; with the passive interposer, wafer thinning and thin-wafer handling costs (for the interposer) are lower because these are not needed for the active chips and thus adds no cost due to yield loss; with the current designs, all the chips are bare; the packaging cost for individual chips is eliminated; more than 90 percent of heat from the 3D IC integration SiP is dissipated from the backside of high-power chips using a thermal interface material and heat spreader/sink; the appearance and footprint of current 3D IC integration SiP designs are very attractive to integrated device manufactures, original equipment manufactures, and electronics manufacturing services (EMS) because they are standard packages; and underfills between the copper-filled TSV interposer and the high-and low-power chips are recommended to reduce creep damage of the lead-free microbump solder joints and prolong their lives. Originality/value -The paper's findings will be very useful to the electronic industry.

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Development of 3-D silicon die stacked package using flip chip technology with micro bump interconnects

Cited by 37 publications

References 5 publications

Wafer Level Solder Bumping and Flip Chip Assembly with Solder Balls Down to 30μm

Wafer Level Solder Bumping and Flip Chip Assembly with Solder Balls Down to 30μm

Low temperature multi-layer wafer level package for chip scale atomic clock (CSAC)

Overview and outlook of through‐silicon via (TSV) and 3D integrations

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