Development of a LEEPL mask: flatness and IP measurements

Abstract

Masks for low energy electron proximity projection lithography (LEEPL TM ) are fabricated starting with 200 mm silicon-on-insulator (SOI) wafers. The effect of the thickness of the buried oxide (BOX) layer of an SOI wafer on its flatness has been investigated. The wafer flatness is found to decrease as the BOX layer becomes thin. When the SOI layer (Si membrane) is not doped by B or P, the membrane has a compressive stress even for a 0.2 µm thick BOX layer.A monitor mask with image placement (IP) marks on a single-large (24 mm square) membrane area has been fabricated, starting with an SOI wafer with an 1.1 µm thick stress-controlled SOI layer and a 0.2 µm thick BOX layer. The internal stress of the membrane was 19 +/-6 MPa (3σ) (tensile), and the membrane flatness was 0.8 µm. An ES chuck for an LSM-IPRO, which holds a mask in the method compatible with that in LEEPL exposure tools, has been installed. Chucking reduced the mask flatness from 22 µm to 10 µm while the membrane flatness was kept less than 1.0 µm. The dynamic repeatability of IP measurement was 7.6 nm (x) and 4.8 nm (y) in 3σ. The IP error of the monitor mask that had only IP marks was 17 nm (x) and 17 nm (y) in 3σ, satisfying the specification of 30 nm or less.

Experimental analysis of image placement accuracy of single-membrane masks for LEEPL

“…Two types of LEEPL stencil masks have been proposed with respect to membrane configurations and strut structures. One is a stencil mask with a single-membrane 4,5 and the other is a complementary stencil mask on strut-supports. 6 Both have merits and demerits.…”