Development of a Smart Metering Microservice Based on Fast Fourier Transform (FFT) for Edge/Internet of Things Environments

Buzachis, Alina; Galletta, Antonino; Celesti, Antonio; Fazio, Maria; Villari, Massimo

doi:10.1109/cfec.2019.8733148

Cited by 11 publications

(7 citation statements)

References 10 publications

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“…Figure 1 shows diverse applications used in each layer. By utilizing pooled, virtualized, and scalable resources, as well as flexible services and scalable storage, the cloud layer facilitates distributed computing, which is bolstered by managed and controlled computing power [2]. The fog layer, which offers virtualized, flexible, and adaptable operation of computation resources, network management, and repository services, is a modern layer that is located closer to the user than the cloud.…”

Section: Iot Architecturesmentioning

confidence: 99%

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Energy Efficient Node Selection in Edge-Fog-Cloud Layered IoT Architecture

Fereira

Ranaweera

Lee

et al. 2023

Sensors

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Internet of Things (IoT) architectures generally focus on providing consistent performance and reliable communications. The convergence of IoT, edge, fog, and cloud aims to improve the quality of service of applications, which does not typically emphasize energy efficiency. Considering energy in IoT architectures would reduce the energy impact from billions of IoT devices. The research presented in this paper proposes an optimization framework that considers energy consumption of nodes when selecting a node for processing an IoT request in edge-fog-cloud layered architecture. The IoT use cases considered in this paper include smart grid, autonomous vehicles, and eHealth. The proposed framework is evaluated using CPLEX simulations. The results provide insights into mechanisms that can be used to select nodes energy-efficiently whilst meeting the application requirements and other network constraints in multi-layered IoT architectures.

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Section: Iot Architecturesmentioning

confidence: 99%

“…It is mainly because each technology has its requirements, architectures, and frameworks. It is important to be cautious when integrating these advanced technologies, to effectively support emerging IOT use cases in a way that saves energy and keeps the cost reasonable [2].…”

Section: Introductionmentioning

confidence: 99%

Energy Efficient Node Selection in Edge-Fog-Cloud Layered IoT Architecture

Fereira

Ranaweera

Lee

et al. 2023

Sensors

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“…Nowadays, power dissipation in VLSI DSP circuits has gained special attention, mainly due to the proliferation of battery‐powered high‐performance devices such as smartphones, portable monitors, and notebooks. Efficient DSP algorithms are applied to process data in smart IoT devices [2]. Among those, the fast Fourier transform (FFT) is one of the most widely employed to transform the signal from the time to the frequency domain.…”

Section: Introductionmentioning

confidence: 99%

Low‐power fast Fourier transform hardware architecture combining a split‐radix butterfly and efficient adder compressors

Ferreira

Paim

Rocha

et al. 2021

IET Computers & Digital Tech

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Fast Fourier transform (FFT) is the most common low‐complexity implementation of the discrete Fourier transform, intensively employed to process real‐world signals in smart sensors for the internet of things. Butterflies play a central role as the FFT computing core data path since it calculates complex terms employing several multipliers. A low‐power FFT hardware architecture combining split‐radix decimation‐in‐time butterfly and 5‐2 adder compressors (ACs) is proposed and implemented. The circuits are described in Verilog hardware description language and synthesized using the Cadence Genus synthesis tool. The circuits are mapped onto a 65‐nm CMOS ST standard cell library. Results reveal that the proposed FFT hardware architecture using the split‐radix butterfly is 13.28% more power efficient than the radix‐4 one. The results further show that, by combining 5‐2 AC within the split‐radix butterfly, our proposal saves up to 43.1% of the total power dissipation considering the whole FFT hardware architecture, compared with the state‐of‐the‐art radix‐4 butterfly employing the adder automatically selected by the logic synthesis tool.

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“…are remotely metered by the manual or semi-manual operation. To improve service efficiency and cost-effectiveness, service providers need more intelligent metering systems [1][2][3]. Automatic meter reading radio frequency modules combined with smart meters to eliminate the expense of human meter readers [4].…”

Section: Introductionmentioning

confidence: 99%

Area and power‐efficient variable‐length fast Fourier transform for MR‐OFDM physical layer of IEEE 802.15.4‐g

Ganjikunta¹,

Sahoo²

2020

IET Computers & Digital Techniques

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The authors present a novel 16/32/64/128-point single-path delay feedback pipeline fast Fourier transform (FFT) architecture targeting the multi-rate and multi-regional orthogonal frequency division multiplexing (MR-OFDM) physical layer of IEEE 802.15.4-g. The proposed FFT architecture employs a mixed-radix algorithm to significantly reduce the number of complex multipliers. It utilises a configurable complex constant multiplier structure instead of a fixed constant multiplier to efficiently conduct W 32 , W 64 , and W 128 twiddle factor multiplication. A hardware-sharing mechanism has also been formulated to reduce the memory space requirements of the proposed 16/32/64/128-point FFT computation scheme. The proposed design is implemented in Xilinx Virtex-5 and Altera's field-programmable gate array devices. For the computation of 128-point FFT, the proposed mixed-radix FFT architecture significantly reduces the hardware cost in comparison with existing FFT architecture. The proposed FFT architecture is also implemented by adopting the 90 nm complementary metal-oxide-semiconductor technology with a supply voltage of 1 V. Post-synthesis results reveal that the design is efficient in terms of gate count and power consumption, compared to earlier reported designs. The proposed variable-length FFT architecture gate count is 22.3K and consumes 3.832 mW, while the word-length is 12-bits and can be efficiently useful for the IEEE 802.15.4-g standard.

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Development of a Smart Metering Microservice Based on Fast Fourier Transform (FFT) for Edge/Internet of Things Environments

Cited by 11 publications

References 10 publications

Energy Efficient Node Selection in Edge-Fog-Cloud Layered IoT Architecture

Energy Efficient Node Selection in Edge-Fog-Cloud Layered IoT Architecture

Low‐power fast Fourier transform hardware architecture combining a split‐radix butterfly and efficient adder compressors

Area and power‐efficient variable‐length fast Fourier transform for MR‐OFDM physical layer of IEEE 802.15.4‐g

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