Development of an analytical model of work function modulated GAA MOSFET for electrostatic performance analysis

To improve the DC and analog/HF performance, a novel dual line tunneling based TFET (DLT-ES-TFET) with elevated source and L-shaped pocket is proposed in this manuscript. In DLT-ES-TFET, the elevated top and extended bottom gates overlapping the source region enhance the line tunneling of charge carriers in both vertical and horizontal directions across the source-pocket interface. TCAD-based simulation results reveal that DLT-ES-TFET offers an improvement of ~47% and ~54% in average subthreshold swing when it is compared with E-VTSFET and L-TFET, respectively. Furthermore, ON-current in DLT-ES-TFET is also found to be improved by an order of ~1 as compared to other two devices. In fact, the L-shaped pocket reduces the corner effects caused by the electric filed crowding across source-channel (S-C) interface, which eventually suppresses the OFF-state leakage in the proposed DLT-ES-TFET. Moreover, enhancement in the charge carriers tunneling across S-C interface leads to a huge increment in the transconductance (~157µs/µm) of DLT-ES-TFET, which further helps in achieving a high cut-off frequency of 12.3GHz. Next, transient response of DLT-ES-TFET-based resistive load inverter suggests a notable improvement in peak over- and under-shoots along with propagation delay as compared to E-VTSFET and L-TFET. Lastly, interface traps and temperature analysis is also found to be in favor of the proposed DLT-ES-TFET.

“…Furthermore, to calculate the cut-off frequency (f T ) [35], it is necessary to determine the total gate capacitance (C gg ) as shown in equation (2).…”

Section: Analysis Of Analog/rf Parametersmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Physics based analysis of a high-performance dual line tunneling TFET with reduced corner effects

Ashok,

Pandey

2024

“…As a result, bulk-silicon transistors are experiencing the same difficulties as MOSFETs due to the presence of Short Channel Effects (SCEs) [1]. To minimize these SCEs, novel device architectures such as Double gate (DG) FET [2][3][4], FinFET [5][6][7], Quadraple gate FET [8,9], and gate all around (GAA) FET [10][11][12][13][14] are introduced in the literature. However, DG FETs poses a challenge in the symmetrical alignment of the front and back gates.…”

Section: Introductionmentioning

confidence: 99%

An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

Mudidhe,

Nistala

2023

The GAA FET has emerged as a promising device due to its excellent control over short-channel effects and improved electrostatic control. This manuscript presents the analytical modelling for the Dual Material Graded Channel (DMGC) Cylindrical GAA FET to characterize the drain current in linear, saturation, as well as subthreshold regions. The model incorporates the effect of supply voltage, radius, and thickness of oxide layer on the device enabling a comprehensive analysis of the device behaviour. The influence of subthreshold swing is also presented. Next, the analysis is extended to investigate the important analog performance parameters that includes transconductance and output conductance. The validation of the analytical model across a wide range of operating conditions with the simulated data is performed and observed to be a close match. Building upon the insights gained from the analytical modelling, a common source amplifier based on the DMGC CGAA FET is designed. The amplifier's performance has been optimized by carefully selecting the biasing conditions and a maximum gain value of 7.745 is achieved. Further, an improvement of 42.28% in output voltage is observed for DMGC in comparison with SMGC making it a promising device for high-performance integrated circuit design.

“…Like conventional MOSFET, NCFET devices also have the same diffusion and drift electron transport mechanism, aiming to drive a higher current than tunnel-based FETs because of the greater channel charge thickness brought by intensified Ψ s at the same off-current. Therefore, NCFET has drawn attention because it can break down the classical minimum limit of Subthreshold Swing, SS = 60 mV/dec with a higher drive current than the conventional MOSFET at the same voltage condition, which is more advantageous while production of new device technology [11][12][13][14]. Further, with the advantage of steep slope value, NCFET has many obstacles during its fabrication process.…”

Section: Introductionmentioning

confidence: 99%

DFT based atomic modeling and temperature analysis on the RF and VTC curve of high-k dielectric layer-assisted NCFET

Mann,

Chaujar

2023

In this report, Density Functional Theory (DFT) based calculation using a Quantum Atomistic Tool Kit (ATK) simulator is done for the hafnia-based ferroelectric material. The band structure, projected density of states (PDOS), and Hartree potential (VH) are taken into account for hafnium oxide (HfO2) and silicon-doped hafnium oxide (Si-doped HfO2). Further, we analyze the temperature variation impact on analog parameters and voltage transfer characteristic (VTC) curve of inverter application of Modified Negative Capacitance Field-Effect-Transistor (NCFET) using the Visual Technology-Computer-Aided-Design (TCAD) simulator. The Modified NCFET structure enhances the DC parameters like leakage current (IOFF) and Subthreshold Swing (SS) compared to the conventional NCFET structure. With the temperature impact, the variation in the parameters of Modified NCFET is discussed at 250 K, 275 K, 300 K, 325 K, and 350 K like transconductance (gm), output conductance (gd), early voltage (VEA) shows the increment as we move from 250 K to 350 K. The short channel effects (SCEs) like Drain Induced Barrier Lowering (DIBL) and Subthreshold Swing (SS) decrease with the temperature fall at 32.98% and 34.74%, respectively. Further, the VTC curve, Noise Margin (NM), and propagation delay of Modified NCFET-based inverter are discussed with the impact of temperature. The propagation delay for the circuit decreased by 67.94% with the rise in the temperature. These factors show that the Modified NCFET-based inverter gives a fast switching performance at high temperatures.