Development of an Enhanced Selective Harmonic Elimination for a Single-Phase Multilevel Inverter with Staircase Modulation

Abstract

A low device switching frequency is recommended for the operation of multilevel inverters (MLIs) to achieve reduced switching losses. Selective harmonic elimination (SHE) and total harmonic distortion (THD) minimization are the two primary switching angle estimation methodologies for low-frequency modulation control. In this regard, a new generalized condition has been developed in this paper for the SHE technique. This original condition will give an output voltage with improved THD in comparison to the conventional SHE technique, while achieving its primary objective of eliminating the specific harmonic content from the output voltage. The proposed condition has been formulated by estimating the error associated with the staircase waveform and the desired sinusoidal output at the fundamental frequency. An infinite harmonic count has been considered for the evaluation of the quality of output, to obtain an accurate THD value without any underestimation. The proposed technique is analyzed, and its critical features are studied in Simulink. The effectiveness of the present work has been also validated by the experimental results.

Sigma-Delta Selective Harmonic Elimination in Cascaded H-Bridge Multilevel Inverters Using FPGA-Enabled Recurrent Neural Network-Newton Raphson Algorithm

“…From Fig. 7, an 11-level output voltage waveform,5 notches are created, and each notch represents angles α1, α2, α3, α4, α5 and for the quarter wave symmetry, the fundamental value of voltage can be obtained using Fourier transform [17], [18].…”