Development of an evaluation model for the design of fault-tolerant solid state mass memory

Cardarilli, G.C.; Marinucci, P.; Salsano, A.

doi:10.1109/iscas.2000.856418

Cited by 8 publications

(5 citation statements)

References 5 publications

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“…Systemmemory cooperative solutions that DRAM consumers can implement to improve memory reliability identify and/or address memory errors before they impact the system at large. Hardware solutions include rank-level ECC [51,53,54,62,63,71,72,81,87,93,101,105,108], rank-level ECC scrubbing [94,221,279,280,315,[315][316][317][318][319], and bit repair techniques [79,86,[320][321][322][323][324][325][326][327]. Software-based approaches include retiring known-bad memory pages [49,60,83,84,88,103], and predicting failures [328][329][330][331][332][333].…”

Section: Study 4: Improving Memory Reliabilitymentioning

confidence: 99%

“…ror models 4 ⃝ based on a previous understanding of DRAM errors (e.g., from past experiments or scientific studies). Examples of such error models include: analytical models based on understanding DRAM failure modes (e.g., sources of runtime faults [51,60,149,[371][372][373]), parametric statistical models that provide useful summary statistics (e.g., lognormal distribution of cell data-retention times [276,277,[374][375][376][377][378][379][380], exponential distribution of the time-in-state of cells susceptible to variable-retention time (VRT) [65,94,150,166,367,[381][382][383][384][385][386][387][388][389]), physics-based simulation models (e.g., TCAD [232,374,[390][391][392] and SPICE models [14,59,78,106,109,283,[393][394][395]), and empirically-determined curves that predict observations well (e.g., single-bit error rates…”

Section: Testing Modelingmentioning

confidence: 99%

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Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Patel

Kim

Shahroodi

et al. 2020

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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Generational improvements to commodity DRAM throughout half a century have long solidified its prevalence as main memory across the computing industry. However, overcoming today's DRAM technology scaling challenges requires new solutions driven by both DRAM producers and consumers. In this paper, we observe that the separation of concerns between producers and consumers specified by industry-wide DRAM standards is becoming a liability to progress in addressing scaling-related concerns.To understand the problem, we study four key directions for overcoming DRAM scaling challenges using system-memory cooperation: (i) improving memory access latencies; (ii) reducing DRAM refresh overheads; (iii) securely defending against the RowHammer vulnerability; and (iv) addressing worsening memory errors. We find that the single most important barrier to advancement in all four cases is the consumer's lack of insight into DRAM reliability. Based on an analysis of DRAM reliability testing, we recommend revising the separation of concerns to incorporate limited information transparency between producers and consumers. Finally, we propose adopting this revision in a two-step plan, starting with immediate information release through crowdsourcing and publication and culminating in widespread modifications to DRAM standards.

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Section: Study 4: Improving Memory Reliabilitymentioning

confidence: 99%

Section: Testing Modelingmentioning

confidence: 99%

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Patel

Kim

Shahroodi

et al. 2020

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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“…Second, the system designer may make predictions from analytical or empirical error models 4 based on a previous understanding of DRAM errors (e.g., from past experiments or scienti c studies). Examples of such error models include: analytical models based on understanding DRAM failure modes (e.g., sources of runtime faults [21,49,123,[271][272][273]), parametric statistical models that provide useful summary statistics (e.g., lognormal distribution of cell data-retention times [190,191,[274][275][276][277][278][279][280]…”

Section: Testing Modelingmentioning

confidence: 99%

“…To address this disparity, system designers have long since developed techniques for adapting unmodi ed commodity DRAM chips to varying system requirements. Examples include: (1) actively identifying and/or mitigating errors to improve reliability [48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65]; (2) exploiting available timing [39,[66][67][68][69][70][71][72] and voltage [73][74][75] margins to reduce memory access latency, power consumption, decrease refresh overheads [22,[76][77][78][78][79][80][81][82]; and (3) mitigating unwanted DRAM data persistence [83][84][85] and read-disturb problems [86][87][88][89][90]. Section 2.1 discusses these proposals in greate...…”

Section: Introductionmentioning

confidence: 99%

A Case for Transparent Reliability in DRAM Systems

Patel¹,

Shahroodi²,

Manglik³

et al. 2022

Preprint

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Mass-produced commodity DRAM is the preferred choice of main memory for a broad range of computing systems due to its favorable cost-per-bit. However, today's systems have diverse system-speci c needs (e.g., performance, energy, reliability) that are di cult to address using one-size-ts-all generalpurpose DRAM. Unfortunately, although system designers can theoretically adapt commodity DRAM chips to meet their particular design goals (e.g., by exploiting slack in access timings to improve performance, or implementing system-level RowHammer mitigations), we observe that designers today lack the necessary insight into commodity DRAM chips' reliability characteristics to implement these techniques in practice. In this work, we make a case for DRAM manufacturers to provide increased transparency into simple device characteristics (e.g., internal row address mapping, cell array organization) that a ect consumer-visible reliability. Doing so has negligible impact on manufacturers given that these characteristics can be reverse-engineered using known techniques; however, it has signi cant bene t for system designers, who can then make informed decisions to be er adapt commodity DRAM to meet modern systems' needs while preserving its cost advantages.To support our argument, we study four ways that system designers can adapt commodity DRAM chips to system-speci c design goals: (1) improving DRAM reliability; (2) reducing DRAM refresh overheads; (3) reducing DRAM access latency; and (4) defending against RowHammer a acks. We observe that adopting solutions for any of the four goals requires system designers to make assumptions about a DRAM chip's reliability characteristics. ese assumptions discourage system designers from using such solutions in practice due to the di culty of both making and relying upon the assumption.We identify DRAM standards as the root of the problem: current standards rigidly enforce a xed operating point with no speci cations for how a system designer might explore alternative operating points. To overcome this problem, we introduce a two-step approach that reevaluates DRAM standards with a focus on transparency of reliability characteristics so that system designers are encouraged to make the most of commodity DRAM technology for both current and future DRAM chips.

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“…For a simple series of systems, in which the 's represent the probability of survival at End Of Life (EOL), we get The above equation has an infinite number of solutions and a procedure that yields a unique or limited number of solutions must be used. For this purpose we use a proprietary optimization tool [23] based on the minimization of an Effort Function, as described in [24]. For the reliability evaluation of the SSMM the reliability model shown in Fig.…”

Section: A Solid State Mass Memory Reliability Evaluationmentioning

confidence: 99%

Fault tolerant solid state mass memory for space applications

Cardarilli

Ottavi

Pontarelli

et al. 2005

IEEE Trans. Aerosp. Electron. Syst.

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Abstract-This paper describes a novel architecture of fault tolerant Solid State Mass Memory (SSMM) for satellite applications. Mass memories with low-latency time, high throughput, and storage capabilities cannot be easily implemented using space qualified components, due to the inevitable technological delay of these kind of components. For this reason, the choice of Commercial Off The Shelf (COTS) components is mandatory for this application. Therefore, the design of an electronic system for space applications, based on commercial components, must match the reliability requirements using system level methodologies [1], [2]. In the proposed architecture error-correcting codes are used to strengthen the commercial Dynamic Random Access Memory (DRAM) chips, while the system controller is developed by applying fault tolerant design solutions. The main features of the SSMM are the dynamic reconfiguration capability, and the high performances which can be gracefully reduced in case of permanent faults, maintaining part of the system functionality. This paper shows the system design methodology, the architecture, and the simulation results of the SSMM. The properties of the building blocks are described in detail both in their functionality and fault tolerant capabilities. A detailed analysis of the system reliability and data integrity is reported. The graceful degradation capability of our system allows different levels of acceptable performances, in terms of active I/O link Interfaces and storage capability. The results also show that the overall reliability of the SSMM is almost the same using different RS coding schemes, allowing a dynamic reconfiguration of the coding to reduce the latency (shorter codewords), or to improve the data integrity (longer codewords). The use of a scrubbing technique can be useful if a high SEU rate is expected, or if the data must be stored for a long period in the SSMM.The reported simulations show the behavior of the SSMM in presence of permanent and transient faults. In fact, we show that the SCU is able to recover from transient faults. On the other hand, using a spare microcontroller also hard faults can be tolerated. The distributed file system confines the unrecoverable fault effects only in a single I/O Interface. In this way, the SSMM maintains its capability to store and read data. The proposed system allows obtaining SSMM characterized by high reliability and high speed due the intrinsic parallelism of the switching matrix.

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Development of an evaluation model for the design of fault-tolerant solid state mass memory

Cited by 8 publications

References 5 publications

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

A Case for Transparent Reliability in DRAM Systems

Fault tolerant solid state mass memory for space applications

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