Development of an FPGA-based gate signal generator for a multilevel inverter

Salim, F.; Azli, Naziha Ahmad

doi:10.1109/peds.2003.1282872

Cited by 5 publications

(2 citation statements)

References 5 publications

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“…The phase voltage consists of N-level inverter. the levels in phase voltage are 2N+1, here N is 1-ϕ inverter cells present in a phase and the number of levels in line voltage are 2M-1, where M is the number of level in phase voltage [8], [9].…”

Section: Three-phase N-level Cascaded H-bridge Multi-level Invertermentioning

confidence: 99%

Analysis and Implementation of Unipolar PWM Strategies for Three Phase Cascade Multilevel Inverter Fed Induction Motor Drive

Bhukya

Kumar

2018

IJAAS

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This paper presents unipolar pulse width modulation technique with sinusoidal sampling pulse width modulation are analyzed for three-phase five-level, seven-level, nine-level and eleven-level cascaded multi-level inverter. The unipolar PWM method offers a good opportunity for the realization of the Three-phase inverter control, it is better to use the unipolar PWM method with single carrier wave compared to two reference waves. In such case the motor harmonic losses will be considerably lower.The necessary calculations for generation of unipolar pulse width modulation strategies have presented in detail. The unipolar SPWM voltage switching scheme is selected in this paper because this method offers the advantages of effectively doubling the switching frequency of the inverter voltage. The cascaded multi level inverter fed induction motor is simulated and compared the total harmonic distroction for all level (five-level, seven-level, nine-level and elevel-level)of the inverter. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.

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Section: Three-phase N-level Cascaded H-bridge Multi-level Invertermentioning

confidence: 99%

Analysis and Implementation of Unipolar PWM Strategies for Three Phase Cascade Multilevel Inverter Fed Induction Motor Drive

Bhukya

Kumar

2018

IJAAS

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“…CPLD had made a revolution in implementing control circuits in the field of gating drives for inverters [10] . Fig.…”

Section: Cpld Implementation Of Control Circuitmentioning

confidence: 99%

Design and Implementation of a Cpld-Based Multilevel Inverter Depending on a Complex Programmable Logic Device (CPLD)

Mohamad-Ali

Hussein

Mohammed

2009

Tikrit j. eng. sci.

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A complex programmable logic device (CPLD) based multilevel inverter has been designed and implemented. The design involves three main parts. The first part is the switching angle generator (SAG), which determines the switching angles from an optimized primitive angle. The second part is the switching pulse generator (SPG), which controls the drive circuit of the inverter. The timing circuit is the third part, which provides the necessary timing for both SAG and SPG. Implementing both SAG and SPG using a CPLD device mean high speed cycle time. Hence an accurate timing for the switching angles is obtained compared to other procedures that uses software for calculating and generating the switching angles, such as microcontroller. MATLAB work space has been used to acquire and analyze the inverter output via the PC sound card. Results of the implemented inverter staircase output voltage, as well as the output frequency spectrum are obtained.

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Implementation of a Single-carrier Multilevel PWM Technique Using Field Programmable Gate Array (FPGA)

Azli

Teng

Lim

2007

2007 7th International Conference on Power Electronics and Drive Systems

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Development of an FPGA-based gate signal generator for a multilevel inverter

Cited by 5 publications

References 5 publications

Analysis and Implementation of Unipolar PWM Strategies for Three Phase Cascade Multilevel Inverter Fed Induction Motor Drive

Analysis and Implementation of Unipolar PWM Strategies for Three Phase Cascade Multilevel Inverter Fed Induction Motor Drive

Design and Implementation of a Cpld-Based Multilevel Inverter Depending on a Complex Programmable Logic Device (CPLD)

Implementation of a Single-carrier Multilevel PWM Technique Using Field Programmable Gate Array (FPGA)

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