Development of low-cost and highly reliable wafer process package

Kazama, Atsushi; Satoh, T.; Yamaguchi, Y.; Anjoh, I.; Nishimura, A.

doi:10.1109/ectc.2001.927681

Cited by 16 publications

(7 citation statements)

References 8 publications

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“…However, another fracture mode with a ductile fracture through the solder ball was also found. This fracture mode, usually seen in previous WLCSP structures [5], [7], [8] was not the desired mode for the SJP-WLCSP since it went against our design concept of releasing the stress caused from the CTE mismatch between silicon chip and FR-4 board. However, only one kind of fracture mode was found in the SiLK-wafer samples.…”

Section: Structurementioning

confidence: 93%

“…After the delamination layer was formed, photopatternable polyimide material used as the bottom insulating layer (BIL) for the metal redistribution traces was spin coated on the wafer and defined. The thickness of the bottom insulating layer was about 5 . The next step was a Ti/Cu/Ni/Au redistribution layer (RDL) formed by Ti/Cu sputtering, Ni electroplating followed by immersion in Au.…”

Section: Structurementioning

confidence: 99%

“…These technologies can be roughly divided according to three major features. One is the use of a soft stress buffer layer (even air gaps) which are formed under the solder bumps to release the shear stress in the solder joints [5]- [8]. Another one of the features was developed by the Fujitsu Company by forming high copper posts to increase the gap between the chip and the PCB in order to reduce the shear stress in the solder joints [9].…”

Section: Introductionmentioning

confidence: 99%

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A Novel Design Structure for WLCSP With High Reliability, Low Cost, and Ease of Fabrication

Chang

Cheng

Shen

et al. 2007

IEEE Trans. Adv. Packag.

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Wafer level chip scale packaging (WLCSP) has some advantages, such as real die size packaging, high electrical performance, and low manufacturing cost. However, because the mechanical reliability of a large die can not be guaranteed due to the coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB), WLCSP technology is still not fully accepted. We have developed a new solder joint protection-WLCSP (SJP-WLCSP) structure with a delamination layer interposed between the top layer of the chip and the bottom insulating layer of the metal redistribution traces. The stress on the solder joints can be released by the cracks forming in the delamination layer, which protects the solder joints from cracking. Since the cracking of the delamination layer is irrelevant to the electrical circuits of the packaging, the packaged integrated circuits (IC) device remains functional. One of the possibilities for processing the SJP-WLCSP was implemented and validated successfully in the SiLK-wafer samples. The board level packaging samples, using the daisy chain resistance measurement passed 1000 cycles of the temperature cycling testing.Index Terms-Delamination layer, memory, wafer level chip scale packaging (WLCSP).

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Section: Structurementioning

confidence: 93%

Section: Structurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Novel Design Structure for WLCSP With High Reliability, Low Cost, and Ease of Fabrication

Chang

Cheng

Shen

et al. 2007

IEEE Trans. Adv. Packag.

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“…The enhancement of solder joint reliability also studied by placing large dummy balls at the outermost corners of the solder joint array [12]. Kazama et al [13] employed the finite element analysis (FEA) to optimize the built-in stressrelaxation layer for reducing the strain of the solder bumps. Gao et al [14] reported a novel design to enhance the board level reliability by incorporating a compliant polymer layer under the UBM.…”

Section: Introductionmentioning

confidence: 99%

Board level temperature cycling study of large array Wafer Level Package

Rahim

Zhou

Fan

et al. 2009

2009 59th Electronic Components and Technology Conference

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The demand for Wafer Level Packages (WLP) has increased significantly due to its smaller package size and lower cost. However, board level reliability of WLP is still a major concern. This study investigates the board level temperature cycle reliability of three very different wafer level package configurations. Comprehensive studies are carried out through temperature cycle test, failure analysis, and finite element modeling. To assess the wafer level package capability and technology limit, the following parameters are considered: WLP structure, array size, ball locations, ball pitch, and temperature cycle profile.Daisy-chain chips are used for this study. Extensive failure analysis was carried out to confirm failure mechanism and quantify the mechanical degradation among different solder joints due to temperature cycle stressing. It is suggested that the primary failure mechanism is solder fatigue. The crack is in bulk solder at package side. The cracks initiate from both sides of the solder joint. The cracks propagate from edge toward the center of the solder ball. The corner balls are most susceptible to solder joint failures. Based on test data, making corner balls electrically not connected improves the WLP reliability by 30%.It is concluded that WLP structure A has superior solder joint reliability compared to B and C. For a given ball array size, smaller pitch gives better solder joint life. The solder joint fatigue life is approximately 1.2 times longer for 2 cycle per hour (cph) conditions than 1 cph temperature cycling condition.

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“…Furthermore, the MCM could be developed at lower cost and in a quicker turnaround time (QTAT) than a SOC, because existing chips were used in its manufacture. The two chips i n the MCM are wafer process packages (WPPs) [1] [2]. Figure 2 shows the crosssectional structure of the WPP.…”

Section: Introductionmentioning

confidence: 99%

Highly reliable and low-cost multi-chip module composed of wafer process packages

Naka

Tanaka

Naitô

53rd Electronic Components and Technology Conference, 2003. Proceedings.

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A high-performance. low-cost, and highly reliable multichip module (MCM) was developed. It is composed of a MPU and a synchronous DRAM [i.e., wafer process packages (WPPs)] on a substrate, To reduce the cost of the MCM, a low-cost FR-4 base is used a substrate on which the WPPs are mounted. Since the mismatch between the thermal expansion coefficients (TEC) of the MPU and DRAM chips and the substrate increases, thermal deformation due to the mismatch may cause cracking of the chip or decrease the life of the solder joints between the MCM and a FR-4 base motherboard.To minimize the stress caused by thermal deformation in the MCM and, thus, to improve its reliability, the structure of the MCM was therefore optimized by finite element analysis (FEA). The FEA results show that thermal stresses in both the chips and the solder bumps are a function of the ratio of chip thickness (tc) and substrate thickness (ts), i.e., tclts, and these stresses decrease when tclts is decreased. Furthermore, thermal-cycling test results show that MCM reliability is assured when tclts is 0.5 or less. A MCM with tclts of 0.4, including a margin of safety, was developed. It was found that the life of this MCM is over 1000 cycles (no chip cracking and no solder joint failure) under thermal-cycling between -55°C and 125°C.

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Development of low-cost and highly reliable wafer process package

Cited by 16 publications

References 8 publications

A Novel Design Structure for WLCSP With High Reliability, Low Cost, and Ease of Fabrication

A Novel Design Structure for WLCSP With High Reliability, Low Cost, and Ease of Fabrication

Board level temperature cycling study of large array Wafer Level Package

Highly reliable and low-cost multi-chip module composed of wafer process packages

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