Development of Novel Fine Line 2.1 D Package with Organic Interposer Using Advanced Substrate-Based Process

Chen, Wei‐Chung; Lee, Chiu-Wen; Kuo, Hung-Chun; Chung, Min-Hua; Wang, Chaung-Chi; Huang, Shang-Kun; Liao, Yen-Sen; Wang, Chen-Chao; Tarng, David

doi:10.1109/ectc.2018.00095

Cited by 12 publications

(1 citation statement)

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“…Utilizing methods such as fan-out/fan-in waferlevel packaging and narrow pitch wire bonds, 2D SiP [32] offers increased integration capabilities and a smaller form factor, making it well-suited for portable devices like smartphones, tablets, and smartwatches. 2.1D Packaging: 2.1D packaging [33] employs an ultra-highdensity redistribution layer (RDL) situated between thin-film layers, characterized by precise metal line width and spacing. Organic interposers can also be employed in this category, providing a cost-efficient means to enhance input and output density for advanced IC packaging.…”

Section: Overview Of Sip Architecturementioning

confidence: 99%

Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration

Sami,

Zhang,

Shuvo

et al. 2024

IEEE Access

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The semiconductor industry has adopted heterogeneous integration (HI), incorporating modular intellectual property (IP) blocks (chiplets) into a unified system-in-package (SiP) to overcome the slowdown in Moore's Law and Dennard scaling and to respond to the increasing demand for advanced integrated circuits (ICs). Despite the manifold benefits of HI, such as enhanced performance, reduced area overhead, and improved yield, this transformation has also led to security vulnerabilities in the SiP supply chain and in-field operations, ranging from chiplet piracy and SiP reverse engineering (RE) to information leakage. Although conventional countermeasures provide the desired robustness for monolithic ICs, they are insufficient for addressing these challenges in the context of HI. To address these concerns, this paper presents a novel root-of-trust architecture, augmenting the process of integration using a centralized chiplet hardware security module (CHSM), aiming to provide comprehensive and robust protection throughout the SiP supply chain and in-field operations. Also, the proposed architecture equipped with the CHSM effectively addresses potential security breaches while providing robust protection against zero-day attacks through its reconfigurable capabilities. Throughout five detailed case studies, this paper performs a comprehensive security analysis to illustrate the resilience of CHSM against contemporary attack scenarios in the HI domain.

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Section: Overview Of Sip Architecturementioning

confidence: 99%