Development of Through Glass Via (TGV) formation technology using electrical discharging for 2.5/3D integrated packaging

Takahashi, Shintaro; Horiuchi, Katsuhiro; Tatsukoshi, Kentaro; Ono, M.; Imajo, Nobuhiko; Mobely, Tim

doi:10.1109/ectc.2013.6575594

Cited by 56 publications

(29 citation statements)

References 2 publications

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“…Through glass via filling by conductive paste filling has been demonstrated for electronic applications by AGC & nMode and further research at universities [7]. The through silicon via filling by conductive paste is in production for silicon solar cells, where the printing process was improved.…”

Section: Paste Fillingmentioning

confidence: 99%

“…Mainly it consists of two steps that focused and controlled electrical discharging created locally molten region of glass, and finally it induced dielectric breakdown together with internal high pressure by Joule heat and ejection of glass. The process is applicable for a lot of types of glass such as fused silica, soda-lime glass, alkali-free glass, alkali-containing glass [5].…”

Section: Discharge For Via Formationmentioning

confidence: 99%

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Development of a high density glass interposer based on wafer level packaging technologies

Topper

Wohrman

Brusberg

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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Currently glass is mainly used as unstructured wafers or panels with the highest market share in glass capping applications. Higher functionality in glass is driven by the applications in RF and Photonics. Since the technologies of via interconnects in Si and glass are completely different, it is challenging to perform a direct and fair comparison. Mainly laser technology and electrical discharge are used for forming the vias into the glass. Slightly modified thin film technologies already in mass production in WLP can be used to fill the vias with a copper metallization. Conformal metallization and full via plating are options. High yield and excellent reliability have been achieved. Generally, due to the lossy nature of silicon and complex polarization mechanism that occurs at the Si-SiO2, TSVs may suffer from severe signal integrity and EMI problems such as huge insertion loss, delay and cross-talk, depending on the Si-resistivity considered. Therefore, regarding the dielectric material, TGVs have significant advantages over TSV, especially when either LRS or MRS is used. In summary TGVs show excellent RF characteristics over TSVs. This has been proven for a test design up to 40 GHz

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Section: Paste Fillingmentioning

confidence: 99%

Section: Discharge For Via Formationmentioning

confidence: 99%

Development of a high density glass interposer based on wafer level packaging technologies

Topper

Wohrman

Brusberg

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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“…Two of these methods are laser based, and the other two have been provided by Asahi Glass and Corning Glass respectively [3,4]. The key to reliable TPV hole formation is to minimize heat and stress accumulation, and prevent micro crack formation.…”

Section: Through Package Vias (Tpv) In Ultra-thin Glassmentioning

confidence: 99%

First demonstration of a surface mountable, ultra-thin glass BGA package for smart mobile logic devices

Sato

Seki

Takagi

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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This paper presents the first demonstration of an ultra-thin glass BGA package that is assembled on to mother board with standard SMT technology. Such a package has many new advances that include ultra-thin glass, high speed through via hole formation and copper metallization, double-side RDL wiring with advanced 3 micron ground rules, and Cu-SnAg microbump assembly of a 10mm silicon test die. Glass, as a package, overcomes the shortcomings of organic packages in bump pitch, CTE mismatch to Si and warpage and silicon interposers in electrical performance and cost. Glass packages are being developed to manufacture both as wafers for improved performance over Si and as panels to improve bump pitch over organic packages. Glass, therefore, is not just a high performance and low volume technology, like silicon interposers, but a pervasive package technology with lower cost, higher performance and thinner than silicon and organic packages. Glass has compelling benefits in thickness and I/O pitch reduction and reliability for one of the highest volume applications, namely, the packaging of high I/O logic devices for smart mobile systems. This paper represents a paradigm shift in ultra-thin packages using large glass panels for future smart mobile and high performance devices, and the first demonstration of 100um thin glass packages with 50-80um chip-level I/O pitch and 18mm x 18mm body size surface mount assembly at 400um pitch. IntroductionGlass packaging started at Georgia Tech and many other R&D groups as a lower cost and higher performance alternative to silicon interposers, due to the low loss and large panel availability of ultra-thin glass [1]. The Georgia Tech team began to demonstrate such an interposer with its industry partners addressing major barriers that include the handling of large, ultra-thin glass panels, forming large number of ultrasmall through vias at small pitch, metallization of these small copper vias without defects and with good adhesion, forming 2-5 micron RDL wiring layers with bump pitch at 20-50 microns, assembly of chips to these brittle substrates, and improving its thermal conductivity. It became clear that glass can be a pervasive platform technology that is both a high performance and very low cost technology. As the glass packaging technology matures and is applied to high volume applications, it should be at the same or lower cost than organic packaging. Glass simplifies the material manufacturing compared to laminates, since FR-4 or low CTE laminates require four different materials and process technologies such as glass fiber, glass and ceramic fillers,

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“…According to the stack-up shown in Fig. 4 and the electrical property of EN-A1 glass from Asahi Glass Company (AGC) [2] and ZEONIF™ ZS-100 polymer from Zeon Cooperation (Zeon) [7] listed in Table I, a 50 Ω CPW line was designed with the center conductor width of 141.025 μm and the gap between conductors of 20 μm. The length of the bottom connection lines was varied as L C =0.6 mm, 1 mm and 1.6 mm, and the top CPW lines were fixed to L IO =0.6 mm.…”

Section: Tgvmentioning

confidence: 99%

“…This paper presents detailed electrical modeling, design and characterization of TPVs in 300 μm thick 3D glass interposers, using a new highthroughput drilling technique, namely the focused electrical discharge method, capable of high throughputs, greater than 1000 vias per second [2]. The focused electrical discharge method is viewed to be a major enabler for high-performance glass interposers, since it is capable of forming high aspectratio TPVs at fine pitch with smooth side wall surfaces, unlike other approaches.…”

Section: Introductionmentioning

confidence: 99%

High-frequency characterization of through package vias formed by focused electrical-discharge in thin glass interposers

Tong

Sato

Takahashi

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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This paper presents the modeling, design, fabrication and characterization, up to 30 GHz, of low loss and high aspectratio 55 μm diameter through package vias (TPVs) in 300 μm thick glass interposers. These TPVs were fabricated using a novel, high-throughput, focused electrical discharge method and low cost panel-based double-side metallization processes. Such a glass interposer is targeted at two emerging applications, (a) large 30 mm to 60 mm body size 2.5D interposers to achieve 28.8 Gbps logic-memory bandwidth and (b) 3D interposers for mm wave applications at 28 GHz local multipoint distribution service (LMDS) for future 5G networks. Accurate measurement of the electrical performance of fine pitch metallized through vias in glass up to 30 GHz and beyond is critical for both these high performance interposer applications. In this paper, two novel characterization methods are applied: 1) the short-circuit-andopen-circuit method and 2) the dual-via-chain method. The resistance and the inductance of a single via are extracted by using a short-circuit structure along with an open-circuit structure. At 10 GHz, the values for the series resistance and inductance have average values of 0.1 Ω and 160 pH respectively. Long dual-via chains were designed to evaluate their performance in insertion loss, delay and eye diagram. The insertion loss achieved with the longest dual-via chain was found to be less than 1 dB/cm up to 30 GHz with only a 6.2 ps delay in the TPVs, and the simulations indicate a wide open eye.

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Development of Through Glass Via (TGV) formation technology using electrical discharging for 2.5/3D integrated packaging

Cited by 56 publications

References 2 publications

Development of a high density glass interposer based on wafer level packaging technologies

Development of a high density glass interposer based on wafer level packaging technologies

First demonstration of a surface mountable, ultra-thin glass BGA package for smart mobile logic devices

High-frequency characterization of through package vias formed by focused electrical-discharge in thin glass interposers

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